A Monitoring-Aware Network-on-Chip Design Flow

Networks-on-chip (NoC) are a scalable interconnect solution for systems on chip and are rapidly becoming reality. Monitoring is a key enabler for debugging or performance analysis and quality-of-service techniques. The NoC design problem and the NoC monitoring problem cannot be treated in isolation. We propose a monitoring-aware NoC design flow able to take into account the monitoring requirements in general. We illustrate our flow with a debug driven monitoring case study of transaction monitoring. By treating the NoC design and monitoring problems in synergy, the area cost of monitoring can be limited to 3-20% in general

[1]  Kees G. W. Goossens,et al.  Cost-performance trade-offs in networks on chip: a simulation-based approach , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[2]  Om Prakash Gangwal,et al.  An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration , 2005 .

[3]  Omar Hammami,et al.  NoC Monitoring Hardware Support for Fast NoC Design Space Exploration and Potential NoC Partial Dynamic Reconfiguration , 2006, 2006 International Symposium on Industrial Embedded Systems.

[4]  van den,et al.  Runtime networks-on-chip performance monitoring , 2005 .

[5]  Jens Sparsø,et al.  A router architecture for connection-oriented service guarantees in the MANGO clockless network-on-chip , 2005, Design, Automation and Test in Europe.

[6]  P.H.N. de With,et al.  Mixed adaptation and fixed-reservation QoS for improving picture quality and resource usage of multimedia (NoC) chips , 2006, 2006 IEEE International Symposium on Consumer Electronics.

[7]  Alain Greiner,et al.  A generic architecture for on-chip packet-switched interconnections , 2000, DATE '00.

[8]  Ran Ginosar,et al.  QNoC: QoS architecture and design process for network on chip , 2004, J. Syst. Archit..

[9]  Kees G. W. Goossens,et al.  An efficient on-chip network interface offering guaranteed services, shared-memory abstraction, and flexible network configuration , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[10]  Kees G. W. Goossens,et al.  An event-based monitoring service for networks on chip , 2005, TODE.

[11]  Diederik Verkest,et al.  Operating-system controlled network on chip , 2004, Proceedings. 41st Design Automation Conference, 2004..

[12]  Drew Wingard,et al.  Socket-Based Design Using Decoupled Interconnects , 2005 .

[13]  Kees G. W. Goossens,et al.  A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification , 2005, Design, Automation and Test in Europe.

[14]  Marco J. G. Bekooij,et al.  A multi-core architecture for incCar digital entertainment , 2005 .

[15]  Azer Bestavros,et al.  A load profiling approach to routing guaranteed bandwidth flows , 1997, Proceedings. IEEE INFOCOM '98, the Conference on Computer Communications. Seventeenth Annual Joint Conference of the IEEE Computer and Communications Societies. Gateway to the 21st Century (Cat. No.98.

[16]  Kees Goossens,et al.  AEthereal network on chip: concepts, architectures, and implementations , 2005, IEEE Design & Test of Computers.

[17]  Luca Benini,et al.  Networks on Chips : A New SoC Paradigm , 2022 .

[18]  Kees G. W. Goossens,et al.  Congestion-Controlled Best-Effort Communication for Networks-on-Chip , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[19]  Sujit Dey,et al.  An Interconnect Architecture for Networking Systems on Chips , 2002, IEEE Micro.

[20]  G. G. Stokes.  "J." , 1890, The New Yale Book of Quotations.

[21]  Axel Jantsch,et al.  The Nostrum backbone-a communication protocol stack for Networks on Chip , 2004, 17th International Conference on VLSI Design. Proceedings..

[22]  W. Dally,et al.  Route packets, not wires: on-chip interconnection networks , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[23]  Srinivasan Murali,et al.  A Methodology for Mapping Multiple Use-Cases onto Networks on Chips , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[24]  Srinivasan Murali,et al.  Bandwidth-constrained mapping of cores onto NoC architectures , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[25]  Kees G. W. Goossens,et al.  Transaction Monitoring in Networks on Chip: The On-Chip Run-Time Perspective , 2006, 2006 International Symposium on Industrial Embedded Systems.

[26]  Radu Marculescu,et al.  Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures , 2003, DATE.

[27]  Kees G. W. Goossens,et al.  A unified approach to constrained mapping and routing on network-on-chip architectures , 2005, 2005 Third IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS'05).

[28]  Kees G. W. Goossens,et al.  NoC monitoring: impact on the design flow , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[29]  Luca Benini,et al.  Xpipes: a latency insensitive parameterized network-on-chip architecture for multiprocessor SoCs , 2003, Proceedings 21st International Conference on Computer Design.

[30]  Kees G. W. Goossens,et al.  A Monitoring-Aware Network-on-Chip Design Flow , 2006, DSD.