A Fast Delay Computation for the Hybrid Structured Clock Network

This paper presents a novel approach to reducing the complexity of the transient linear circuit analysis for a hybrid structured clock network. Topology reduction is first used to reduce the complexity of the circuits and a preconditioned Krylov-subspace iterative method is then used to perform the nodal analysis on the reduced circuits. By proper selection of the simulation time step and interval based on Elmore delays, the delay of the clock signal between the clock source and the sink node as well as the clock skews between the sink nodes can be computed efficiently and accurately. Our experimental results show that the proposed algorithm is two orders of magnitude faster than HSPICE without loss of accuracy and stability. The maximum error is within 0.4% of the exact delay time.

[1]  Richard P. Brent,et al.  An Algorithm with Guaranteed Convergence for Finding a Zero of a Function , 1971, Comput. J..

[2]  Madhav P. Desai,et al.  Sizing of clock distribution networks for high performance CPU chips , 1996, DAC '96.

[3]  Anthony Vannelli,et al.  Interconnection modelling using distributed RLC models , 2003, The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings..

[4]  Charlie Chung-Ping Chen,et al.  Future SoC design challenges and solutions , 2002, Proceedings International Symposium on Quality Electronic Design.

[5]  A. Ruehli.  Equivalent Circuit Models for Three-Dimensional Multiconductor Systems , 1974 .

[6]  Sachin S. Sapatnekar,et al.  Hybrid structured clock network construction , 2001, IEEE/ACM International Conference on Computer Aided Design. ICCAD 2001. IEEE/ACM Digest of Technical Papers (Cat. No.01CH37281).

[7]  Yehea I. Ismail.  Improved model-order reduction by using spacial information in moments , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[8]  Yici Cai,et al.  A fast delay analysis algorithm for the hybrid structured clock network , 2004, IEEE International Conference on Computer Design: VLSI in Computers and Processors, 2004. ICCD 2004. Proceedings..

[9]  K.A. Jenkins,et al.  A clock distribution network for microprocessors , 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).

[10]  Lawrence T. Pileggi,et al.  Asymptotic waveform evaluation for timing analysis , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[11]  Alina Deutsch,et al.  Designing the best clock distribution network , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

[12]  Lawrence T. Pileggi,et al.  RICE: rapid interconnect circuit evaluation using AWE , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Lawrence T. Pileggi,et al.  PRIMA: passive reduced-order interconnect macromodeling algorithm , 1998, 1997 Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[14]  Charlie Chung-Ping Chen,et al.  Efficient large-scale power grid analysis based on preconditioned Krylov-subspace iterative methods , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).