'Zone-refining' techniques for IC layout compaction

Zone-refining refers to a technique that forms a basis for layout compaction algorithms intermediate between one-dimensional (1-D) compactors and two-dimensional (2-D) placement techniques. An expanded zone in which 2-D refinement techniques are employed is repeatedly swept across the layout in different directions. The basic principle is reviewed and the computational complexity of zone refining is analyzed. The difficulties that had to be overcome in making the basic concept useful for compaction of integrated circuit layouts is discussed. One implementation is described, and some of the tradeoffs made and data structures used to obtain an efficient compactor are examined. The scope of possibilities for other implementations are discussed. >

[1]  G. Chartrand,et al.  Graphs & Digraphs , 1986 .

[2]  Mark Horowitz,et al.  Generating Incremental VLSI Compaction Spacing Constraints , 1987, 24th ACM/IEEE Design Automation Conference.

[3]  Christopher Kingsley.  A Hiererachical, Error-Tolerant Compactor , 1984, 21st Design Automation Conference Proceedings.

[4]  Alberto Sangiovanni-Vincentelli,et al.  Two-Dimensional Compaction by 'Zone Refining' , 1986, DAC 1986.

[5]  R. C. Mosteller,et al.  2-D Compaction -- A Monte Carlo Method , 1987 .

[6]  Chak-Kuen Wong,et al.  An algorithm for optimal two-dimensional compaction of VLSI layouts , 1983, Integr..

[7]  Randy Lee Brown.  Multiple Storage Quad Trees: A Simpler Faster Alternative to Bisector List Quad Trees , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Y.E. Cho.  A Subjective Review of Compaction , 1985, 22nd ACM/IEEE Design Automation Conference.

[9]  Neil Weste.  Virtual grid symbolic layout , 1981, DAC '81.

[10]  C. D. Gelatt,et al.  Optimization by Simulated Annealing , 1983, Science.

[11]  Chak-Kuen Wong,et al.  An Algorithm to Compact a VLSI Symbolic Layout with Mixed Constraints , 1983, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[12]  F. Miller Maley,et al.  Single-layer wire routing , 1987 .

[13]  Scott Kirkpatrick,et al.  Global Wiring by Simulated Annealing , 1983, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[14]  Chak-Kuen Wong,et al.  An Algorithm to Compact a VLSI Symbolic Layout with Mixed Constraints , 1983, 20th Design Automation Conference Proceedings.

[15]  John K. Ousterhout,et al.  Corner Stitching: A Data-Structuring Technique for VLSI Layout Tools , 1984, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[16]  Wayne Wolf,et al.  Two-dimensional compaction strategies , 1984 .

[17]  Alberto L. Sangiovanni-Vincentelli,et al.  Two-Dimensional Compaction by 'Zone Refining' , 1986, 23rd ACM/IEEE Design Automation Conference.

[18]  Hiroyuki Watanabe,et al.  Graph-Optimization Techniques for IC Layout and Compaction , 1983, 20th Design Automation Conference Proceedings.

[19]  F. M. Maley.  COMPACTION WITH AUTOMATIC JOG INTRODUCTION , 1986 .