An LDPC Decoder With Time-Domain Analog and Digital Mixed-Signal Processing

Time-domain analog and digital mixed-signal processing (TD-AMS) is presented. Analog computation is more energy- and area-efficient at the cost of its limited accuracy, whereas digital computation is more versatile and derives greater benefits from technology scaling. Besides, design automation tools for digital circuits are much more sophisticated than those for analog circuits. TD-AMS exploits both advantages, and is a solution better suited to implementing a system on chip including functions for which high computational accuracy is not required, such as error correction, image processing, and machine learning. As an example, a low-density parity-check (LDPC) code decoder with the technique is implemented in 65 nm CMOS and achieves the best reported efficiencies of 10.4 pJ/bit and 6.1 Gbps/mm2.

[1]  Robert G. Gallager,et al.  Low-density parity-check codes , 1962, IRE Trans. Inf. Theory.

[2]  Makoto Nagata,et al.  A PWM signal processing core circuit based on a switched current integration technique , 1998, IEEE J. Solid State Circuits.

[3]  K. Muhammad,et al.  All-digital PLL and transmitter for mobile phones , 2005, IEEE Journal of Solid-State Circuits.

[4]  C. Plett,et al.  A 0.18-$muhbox m$CMOS Analog Min-Sum Iterative Decoder for a (32,8) Low-Density Parity-Check (LDPC) Code , 2006, IEEE Journal of Solid-State Circuits.

[5]  J.W. Haslett,et al.  A Fine Resolution TDC Architecture for Next Generation PET Imaging , 2007, IEEE Transactions on Nuclear Science.

[6]  Eric A. M. Klumperink,et al.  A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[7]  Harry Veendrick.  Nanometer CMOS ICs: From Basics to ASICs , 2008 .

[8]  Harry J.M. Veendrick,et al.  Nanometer CMOS ICs , 2008 .

[9]  Bill Bradley,et al.  Low power logic for statistical inference , 2010, 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED).

[10]  Shie Mannor,et al.  A Min-Sum Iterative Decoder Based on Pulsewidth Message Encoding , 2010, IEEE Transactions on Circuits and Systems II: Express Briefs.

[11]  John R. Barry,et al.  Low-Power Discrete Fourier Transform for OFDM: A Programmable Analog Approach , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

[12]  Ming Gu,et al.  An adaptive analog low-density parity-check decoder based on margin propagation , 2011, 2011 IEEE International Symposium of Circuits and Systems (ISCAS).

[13]  Shuhei Tanakamaru,et al.  Over-10×-extended-lifetime 76%-reduced-error solid-state drives (SSDs) with error-prediction LDPC architecture and error-recovery scheme , 2012, 2012 IEEE International Solid-State Circuits Conference.

[14]  Ming Gu,et al.  Synthesis of Bias-Scalable CMOS Analog Computational Circuits Using Margin Propagation , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.

[15]  David Blaauw,et al.  A 1.6-mm2 38-mW 1.5-Gb/s LDPC decoder enabled by refresh-free embedded DRAM , 2012, 2012 Symposium on VLSI Circuits (VLSIC).

[16]  Shyh-Jye Jou,et al.  A 5.79-Gb/s Energy-Efficient Multirate LDPC Codec Chip for IEEE 802.15.3c Applications , 2012, IEEE Journal of Solid-State Circuits.

[17]  B. Sadhu,et al.  A 5GS/s 12.2pJ/conv. analog charge-domain FFT for a software defined radio receiver front-end in 65nm CMOS , 2012, 2012 IEEE Radio Frequency Integrated Circuits Symposium.

[18]  A. R. Abolfazli,et al.  TS-LDPC analog decoding based on the Min-Sum algorithm , 2012, 2012 26th Biennial Symposium on Communications (QBSC).

[19]  Kobayashi Hiroyuki,et al.  An LDPC Decoder with Time Domain Analog and Digital Mixed Signal Processing , 2013 .

[20]  Hiroyuki Kobayashi,et al.  A 10.4pJ/b (32, 8) LDPC decoder with time-domain analog and digital mixed-signal processing , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.