A High-Performance Body-Tied FinFET Bandgap Engineered SONOS (BE-SONOS) for nand-Type Flash Memory
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Rich Liu | Ya-Chin King | Tzu-Hsuan Hsu | Kuang-Yeu Hsieh | Chih-Yuan Lu | Jung-Yu Hsieh | E. Lai | Y. King | K. Hsieh | Chih-Yuan Lu | H. Lue | T. Hsu | J. Hsieh | Hang Ting Lue | E.-K. Lai | Rich Liu
[1] Tang-Hsuan Chung,et al. 20nm gate bulk-finFET SONOS flash , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..
[2] Chang Woo Oh,et al. Fully integrated SONOS flash memory cell array with BT (body tied)-FinFET structure , 2006 .
[3] Donggun Park,et al. Fully integrated SONOS flash memory cell array with BT (body tied)-FinFET structure , 2006, IEEE Transactions on Nanotechnology.
[4] J. Bu,et al. On the go with SONOS , 2000 .
[5] Bin Yu,et al. FinFET scaling to 10 nm gate length , 2002, Digest. International Electron Devices Meeting,.
[6] Joo-Tae Moon,et al. 8 Gb MLC (multi-level cell) NAND flash memory using 63 nm process technology , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..
[7] Tahone Yang,et al. Reliability Model of Bandgap Engineered SONOS (BE-SONOS) , 2006, 2006 International Electron Devices Meeting.
[8] Y. Shih,et al. BE-SONOS: A bandgap engineered SONOS with excellent performance and reliability , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..
[9] Rich Liu,et al. A BE-SONOS (Bandgap Engineered SONOS) NAND for Post-Floating Gate Era Flash Memory , 2007, 2007 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).
[10] Kinam Kim,et al. Technology for sub-50nm DRAM and NAND flash manufacturing , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..
[11] M. Janai. Data retention, endurance and acceleration factors of NROM devices , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..
[12] H. Reisinger,et al. Sub-40nm tri-gate charge trapping nonvolatile memory cells for high-density applications , 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..
[13] Seung Beom Kim,et al. SONOS-Type FinFET Device Using P+ Poly-Si Gate and High-k Blocking Dielectric Integrated on Cell Array and GSL/SSL for Multi-Gigabit NAND Flash Memory , 2006, 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers..
[14] U. Chung,et al. Fabrication of body-tied FinFETs (Omega MOSFETs) using bulk Si wafers , 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).
[15] Hang-Ting Lue,et al. Novel soft erase and re-fill methods for a P/sup +/-poly gate nitride-trapping non-volatile memory device with excellent endurance and retention properties , 2005, 2005 IEEE International Reliability Physics Symposium, 2005. Proceedings. 43rd Annual..
[16] H. Reisinger,et al. 20 nm tri-gate SONOS memory cells with multi-level operation , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..