Electrical Model of Microcontrollers for the Prediction of Electromagnetic Emissions

This work presents a new methodology to derive the equivalent circuit of the parasitic paths that propagate switching noise in mixed-signals integrated circuits and that usually lead to unintended crosstalk and electromagnetic emission issues. The methodology is based on small-signal analyses performed at the individual analog and digital microcontroller building block level, on electromagnetic simulations carried out to describe the power supply network at the chip- and at the package-level and on the analysis of the chip layout and process technology data to model the parasitic coupling paths through the semiconductor substrate. The electrical model of microcontrollers generated according to this methodology, consists of a low-complex and linear netlist that provides insight regarding the relationships between the design parameters and noise propagation paths in the early design phases, through simulations in a SPICE-like environment. The proposed approach does not rely on experimental test results. In this paper, the electric model of an 8 bit microcontroller, which validity has been proved by scattering parameter and conducted emission measurements, is derived.

[1]  P. Larsson Resonance and damping in CMOS circuits with on-chip decoupling capacitance , 1998 .

[2]  Eby G. Friedman,et al.  Power Distribution Networks with On-Chip Decoupling Capacitors , 2007 .

[3]  P.S. Crovetti,et al.  A Linear Voltage Regulator Model for EMC Analysis , 2007, IEEE Transactions on Power Electronics.

[4]  P. Yang,et al.  Multilevel metal capacitance models for CAD design synthesis systems , 1992, IEEE Electron Device Letters.

[5]  Junwu Tao,et al.  Modeling the Electromagnetic Emission of a Microcontroller Using a Single Model , 2008, IEEE Transactions on Electromagnetic Compatibility.

[6]  D. J. Allstot,et al.  Computer-aided design considerations for mixed-signal coupling in RF integrated circuits , 1998 .

[7]  Robert G. Meyer,et al.  Modeling and analysis of substrate coupling in integrated circuits , 1996 .

[8]  Guido Torelli,et al.  A Simple Model for Digital/Analog Crosstalk Simulation in Deep Submicron CMOS Technology , 2001 .

[9]  Francesc Moll,et al.  Interconnection noise in VLSI circuits , 2003 .

[10]  J. S. Neely,et al.  Interconnect and circuit modeling techniques for full-chip power supply noise analysis , 1998 .

[11]  Yoshitaka Toyota,et al.  Power current modeling of IC/LSI with load dependency for EMI simulation , 2003, 2003 IEEE Symposium on Electromagnetic Compatibility. Symposium Record (Cat. No.03CH37446).

[12]  Dake Liu,et al.  Power consumption estimation in CMOS VLSI chips , 1994, IEEE J. Solid State Circuits.

[13]  Paolo Stefano Crovetti,et al.  Efficient BEM-based substrate network extraction in silicon SoCs , 2008, Microelectron. J..

[14]  D. Blaauw,et al.  Impact of low-impedance substrate on power supply integrity , 2003, IEEE Design & Test of Computers.

[15]  Masaaki Yamada,et al.  EMI-noise analysis under ASIC design environment , 1999, ISPD '99.

[16]  Lawrence E. Crooks,et al.  Noise reduction techniques in electronic systems (2nd ed.), Henry W. Ott. Wiley‐Interscience, New York. 1988 , 1989 .

[17]  T. Steinecke,et al.  VLSI IC emission models for system simulation , 2008, 2008 Asia-Pacific Symposium on Electromagnetic Compatibility and 19th International Zurich Symposium on Electromagnetic Compatibility.

[18]  Rajendran Panda,et al.  Model and analysis for combined package and on-chip power grid simulation , 2000, ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514).

[19]  Avinoam Kolodny,et al.  On-Chip Power Distribution Grids With Multiple Supply Voltages for High-Performance Integrated Circuits , 2008, IEEE Trans. Very Large Scale Integr. Syst..

[20]  A. Kolodny,et al.  Leveraging symbiotic on-die decoupling capacitance , 2005, IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging, 2005..

[21]  Eby G. Friedman,et al.  Efficient Distributed On-Chip Decoupling Capacitors for Nanoscale ICs , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[22]  Eby G. Friedman,et al.  Decoupling capacitors for multi-voltage power distribution systems , 2006, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[23]  Kamran Eshraghian,et al.  Principles of CMOS VLSI Design: A Systems Perspective , 1985 .

[24]  T.H. Hubing,et al.  The Electromagnetic Compatibility of Integrated Circuits—Past, Present, and Future , 2009, IEEE Transactions on Electromagnetic Compatibility.

[25]  Lijun Han,et al.  A Nonlinear Microcontroller Power Distribution Network Model for the Characterization of Immunity to Electrical Fast Transients , 2009, IEEE Transactions on Electromagnetic Compatibility.

[26]  Marc Belleville,et al.  Inductance and capacitance analytic formulas for VLSI interconnects , 1996 .