Design of Scaler with Reduced Hardware Complexity

Due to the use of Farrow structure,area of four-point piecewise-parabolic interpolator was reduced to 30%,compared with the one implemented directly.With particular characteristics of Farrow structure in consideration,a flexible coefficient generation method was also proposed.Meanwhile,a new memory addressing scheme saves 12.5% area of buffers at least in vertical orientation.The total design was implemented using FPGA,and the scaler was embedded as an IP in a video format conversion chip.