A fast and accurate validation technique for operating system in multi-processor system-on-chip design

Modern electronic system design is based on integrating heterogeneous components (μP, DSP, ASIC, memories, buses, MEMS, MOEMS, etc.) on a single chip. These highly integrated systems are commonly known as System-on-Chip (SoC). System validation by HW-SW co-simulation can enhance the quality of a System-on-Chip (SoC) design. In this paper, we present a SW simulation model for both operating system and application. The model gives fast simulation exploiting the native execution of OS and application SW. For accurate simulation, it enables timing simulation with several levels of timing delay granularities, which enables the designer to have trade-off between simulation speed and accuracy. For timing delay estimation, the OS and application SW codes are compiled for a target processor and the delay of each assembly instruction is calculated. Then, according to the granularity of timing delay chosen by the designer, delays are annotated into the OS and application SW codes. For HW-SW co-simulation of the entire SoC, the execution of proposed model, we present a bus functional model (BFM). The BFM exchanges simulation events between HW and SW simulation while synchronizing their timing simulation. The technique proposed in this paper could be useful for complex heterogeneous system validation and design.