Switching performance analyses of gate material and gate dielectric engineered TFET architectures and impact of interface oxide charges

In this work performance investigation of three different Double Gate n-type TFET architectures i.e. Dual material Gate (DMG) TFET, Hetero-Dielectric (H-D) TFET and Dual Material Hetero-Dielectric (DMG H-D) TFET has been performed for Digital Circuit Applications. Moreover, a comparative study among these three aforementioned device architectures has been made in terms of performance metrics such as Total gate Capacitance (C<sub>gg</sub>), Miller capacitance (C<sub>gd</sub>), fall propagation delay (t<sub>pHL</sub>) and peak overshoot voltage (V<sub>p</sub>). In this regard, exhaustive simulations have been done through Atlas Device Simulator. Furthermore, the impact of metal gate (M1) work function and length L<sub>1</sub> variation over device switching characteristics has also been observed. Impact of Interface oxide charges (positive and negative) on the transient behavior, threshold voltage, I<sub>on</sub>, I<sub>off</sub>, I<sub>on</sub>/I<sub>off</sub> has also been studied for all three device architectures. It has been investigated that DMG H-D TFET which is the proposed architecture outperforms other devices i.e. DMG TFET and H-D TFET in terms of comparatively lower value of t<sub>pHL</sub>, V<sub>p</sub> and miller capacitance C<sub>gd</sub>.

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