On-chip global signaling by wave pipelining

This work discusses the signaling performance of wave pipelining over on-chip transmission lines comparing conventional signaling with CMOS static repeater insertion. We experimentally reveal that the wave pipelining over on-chip transmission lines is about ten times superior in the maximum throughput, latency and dissipates several times less energy per bit compared with the conventional signaling, whereas the required interconnect resource is comparable.

[1]  William J. Dally,et al.  Digital systems engineering , 1998 .

[2]  Daniel C. Edelstein,et al.  On-chip wiring design challenges for gigahertz operation , 2001, Proc. IEEE.

[3]  S. Tam,et al.  Clock generation and distribution for the 130-nm Itanium/sup /spl reg// 2 processor with 6-MB on-die L3 cache , 2004, IEEE Journal of Solid-State Circuits.

[4]  M. Mizuno,et al.  On-chip multi-GHz clocking with transmission lines , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[5]  David A. B. Miller,et al.  Limit to the Bit-Rate Capacity of Electrical Interconnects from the Aspect Ratio of the System Architecture , 1997, J. Parallel Distributed Comput..

[6]  Jose E. Schutt-Aine,et al.  Optimal transient simulation of transmission lines , 1996 .

[7]  H. A. Affel,et al.  Transmission lines , 1934 .

[8]  Sachin S. Sapatnekar,et al.  A method for correcting the functionality of a wire-pipelined circuit , 2004, Proceedings. 41st Design Automation Conference, 2004..

[9]  Himanshu Kaul,et al.  Low-power on-chip communication based on transition-aware global signaling (TAGS) , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[10]  Yu Hen Hu,et al.  Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining , 2004, Proceedings. 41st Design Automation Conference, 2004..

[11]  John Lillis,et al.  Interconnect Analysis and Synthesis , 1999 .

[12]  Pingshan Wang,et al.  Pulsed wave interconnect , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[13]  Masanori Hashimoto,et al.  Performance limitation of on-chip global interconnects for high-speed signaling , 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).