UNIVERSITY OF CALIFORNIA Santa Barbara Wireless Data Interface for Cryogenic Imaging Arrays
暂无分享,去创建一个
[1] G. K. Reeves,et al. Obtaining the specific contact resistance from transmission line model measurements , 1982, IEEE Electron Device Letters.
[2] Walter S. Scott,et al. Magic: A VLSI Layout System , 1984, 21st Design Automation Conference Proceedings.
[3] J.E. Mazo,et al. Digital communications , 1985, Proceedings of the IEEE.
[4] D. C. Bunday. Advanced Digital Communications , 1987 .
[5] M. Deen. Digital characteristics of CMOS devices at cryogenic temperatures , 1989 .
[6] Christer Svensson,et al. High-speed CMOS circuit technique , 1989 .
[7] Stephen I. Long,et al. Gallium arsenide digital integrated circuit design , 1990 .
[8] C. Svensson,et al. Fast CMOS nonbinary divider and counter , 1993 .
[9] Robert G. Meyer,et al. Analysis and Design of Analog Integrated Circuits , 1993 .
[10] John McNeill,et al. Jitter in ring oscillators , 1994, Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94.
[11] C. Svensson,et al. Impact of clock slope on true single phase clocked (TSPC) CMOS circuits , 1994, IEEE J. Solid State Circuits.
[12] Qiuting Huang,et al. Speed optimization of edge-triggered CMOS circuits for gigahertz single-phase clocks , 1996 .
[13] Byungsoo Chang,et al. A 1.2 GHz CMOS dual-modulus prescaler using new dynamic D-type flip-flops , 1996 .
[14] Christer Svensson,et al. New single-clock CMOS latches and flipflops with improved speed and power savings , 1997 .
[15] Miryeong Song,et al. New understanding of LDD CMOS hot-carrier degradation and device lifetime at cryogenic temperatures , 1997, 1997 IEEE International Reliability Physics Symposium Proceedings. 35th Annual.
[16] Thomas H. Lee,et al. The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES , 2003 .
[17] Sten Hellström. ESD ― The Scourge of Electronics , 1998 .
[18] Kenji Taniguchi,et al. An implementation technique of dynamic CMOS circuit applicable to asynchronous/synchronous logic , 1998, ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187).
[19] S. Kim,et al. Double precharge TSPC for high-speed dual-modulus prescaler , 1999, ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361).
[20] H. F. Ragaie,et al. On the design and sensitivity of RC sequence asymmetric polyphase networks in RF integrated transceivers , 1999, ISCAS'99. Proceedings of the 1999 IEEE International Symposium on Circuits and Systems VLSI (Cat. No.99CH36349).
[21] Tatsuo Itoh,et al. Integrated-antenna push-pull power amplifiers , 1999 .
[22] M. Borremans,et al. The optimization of GHz integrated CMOS quadrature VCO's based on a poly-phase filter loaded differential oscillator , 2000, 2000 IEEE International Symposium on Circuits and Systems. Emerging Technologies for the 21st Century. Proceedings (IEEE Cat No.00CH36353).
[23] A. Hastings. The Art of Analog Layout , 2000 .
[24] S. Kimura,et al. Gate length scalability of n-MOSFETs down to 30 nm: Comparison between LDD and non-LDD structures , 2000 .
[25] A. Demir,et al. Phase noise in oscillators: a unifying theory and numerical methods for characterization , 2000 .
[26] Kyoung-Rok Cho,et al. A CMOS dual-modulus prescaler based on a new charge sharing free D-flip-flop , 2001, Proceedings 14th Annual IEEE International ASIC/SOC Conference (IEEE Cat. No.01TH8558).
[27] Asad A. Abidi,et al. CMOS mixers and polyphase filters for large image rejection , 2001, IEEE J. Solid State Circuits.
[28] Chih-Ming Hung,et al. Intra-chip wireless interconnect for clock distribution implemented with integrated antennas, receivers, and transmitters , 2002, IEEE J. Solid State Circuits.
[29] S. Banerjee,et al. Improved hot-carrier and short-channel performance in vertical nMOSFETs with graded channel doping , 2002 .
[30] A. Hajimiri,et al. A CMOS differential noise-shifting Colpitts VCO , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).