Bit-level pipelined 2-D digital filters for real-time image processing

Bit-level systolic arrays for real-time 2-D FIR and IIR (finite and infinite impulse response) filters are presented. Two-dimensional iteration and retiming techniques are depicted to illustrate block pipeline 2-D IIR filters, which guarantee high-throughput operation for real-time applications. The block (parallel) systolic architectures are refined down to the bit level. This increases the filter's throughput rate and decreases the filter's development and manufacturing costs. The AP figure is improved from O(N/sup 2/W/sup 3/) for the previous design to O(N/sup 2/W/sup 2/), i.e. by a factor of O(W), where W is the word length. Pipelining at the bit rate level is the major reason for this improvement. Another advantage of the proposed design is that it has simpler wire routing and control circuitry. In summary, these systolic-array realizations are more cost effective; more regular structurally; composed of bit-level cells and latches; and fully pipelined at the bit level. >

[1]  James B. Angell,et al.  Enhancing Testability of Large-Scale Integrated Circuits via Test Points and Additional Logic , 1973, IEEE Transactions on Computers.

[2]  Bede Liu,et al.  A new hardware realization of digital filters , 1974 .

[3]  S. Mitra,et al.  Realizations of two-dimensional recursive digital filters , 1975 .

[4]  S. Mitra,et al.  Decision methods and realization of 2-D digital filters using minimum number of delay elements , 1980 .

[5]  Peter M. Kogge,et al.  The Architecture of Pipelined Computers , 1981 .

[6]  W. Steenaart,et al.  High speed stored product recursive digital filters , 1982 .

[7]  John G. McWhirter,et al.  Completely iterative, pipelined multiplier array suitable for VLSI , 1982 .

[8]  Charles E. Leiserson,et al.  Optimizing Synchronous Circuitry by Retiming (Preliminary Version) , 1983 .

[9]  T. Aboulnasr,et al.  2-D state-space realizations with fewer multipliers and invariant norms , 1983 .

[10]  Dan E. Dudgeon,et al.  Multidimensional Digital Signal Processing , 1983 .

[11]  S. Mitra,et al.  Block implementation of two-dimensional digital filters , 1983 .

[12]  Basil G. Mertzios.  Block realization of 2-D, IIR digital filters , 1984 .

[13]  2-D state-space digital filters with fewer multipliers , 1986, 1985 24th IEEE Conference on Decision and Control.

[14]  Edward A. Lee,et al.  Fast recursive filtering with multiple slow processing elements , 1985 .

[15]  Henry Fuchs,et al.  PIXEL-PLANES: BUILDING A VLSI-BASED GRAPHIC SYSTEM. , 1985 .

[16]  M. Azimi-Sadjadi,et al.  Two-dimensional block processors - Structures and implementations , 1986 .

[17]  Anastasios N. Venetsanopoulos,et al.  A fast filter for real-time image processing , 1986 .

[18]  P.R. Cappello,et al.  Computer-aided design of VLSI FIR filters , 1987, Proceedings of the IEEE.

[19]  Anastasios N. Venetsanopoulos,et al.  High-speed architectures for digital image processing , 1987 .

[20]  John W. Woods,et al.  A video rate architecture for a fully recursive two-dimensional filter , 1987, ICASSP '87. IEEE International Conference on Acoustics, Speech, and Signal Processing.

[21]  George A. Lampropoulos,et al.  A new realization fo 2-D digital filters , 1987, IEEE Trans. Acoust. Speech Signal Process..

[22]  Stephen I. Long,et al.  System Architecture of a Gallium Arsenide One-Gigahertz Digital IC Tester , 1987, Computer.

[23]  W. Alexander,et al.  Block realization of multidimensional IIR digital filters and its finite word effects , 1987 .

[24]  Peter R. Cappello,et al.  Computer-aided design of VLSI second-order sections , 1987, ICASSP '87. IEEE International Conference on Acoustics, Speech, and Signal Processing.

[25]  M. Ismail.  Realization of two-dimensional recursive digital filters using the mixed Cauer form† , 1988 .

[26]  R. Gnanasekaran.  2-D filter implementations for real-time signal processing , 1988 .

[27]  W. Steenaart,et al.  Real-time systolic array processor for 2-D spatial filtering , 1988 .

[28]  Peter R. Cappello,et al.  Application-specific CAD of VLSI second-order sections , 1988, IEEE Trans. Acoust. Speech Signal Process..

[29]  Mahmood R. Azimi-Sadjadi,et al.  Parallel and pipeline architectures for 2-D block processing , 1989 .

[30]  Maher A. Sid-Ahmed.  A systolic realization for 2-D digital filters , 1989, IEEE Trans. Acoust. Speech Signal Process..

[31]  Keshab K. Parhi,et al.  Pipeline interleaving and parallelism in recursive digital filters. I. Pipelining using scattered look-ahead and decomposition , 1989, IEEE Trans. Acoust. Speech Signal Process..

[32]  Cheng-Wen Wu,et al.  Block multipliers unify bit-level cellular multiplications , 1989 .

[33]  Keshab K. Parhi,et al.  Concurrent architectures for two-dimensional recursive digital filtering , 1989 .

[34]  Keshab K. Parhi,et al.  Pipeline interleaving and parallelism in recursive digital filters. II. Pipelined incremental block filtering , 1989, IEEE Trans. Acoust. Speech Signal Process..

[35]  W. Steenaart,et al.  VLSI realizable high performance structures for real-time state-space filtering , 1989 .

[36]  R. Unbehauen,et al.  Implementation of 2-D filters for real-time processing , 1989 .

[37]  Peter R. Cappello,et al.  Easily Testable Iterative Logic Arrays , 1990, IEEE Trans. Computers.

[38]  F.J. Taylor,et al.  Multiplier policies for digital signal processing , 1990, IEEE ASSP Magazine.

[39]  Realization of 2-D state-space filters with fewer multipliers , 1990 .