SET-based nano-circuit simulation and design method using HSPICE

Abstract This paper presents a simulation and design method for complementary SET-based nano-circuits from a practical circuit design point of view. HSPICE behavioral implementation of modified Lientschnig's SET model based on the orthodox theory and the Birth–Death Markov chain is demonstrated and verified with Coulomb characteristics. It shows reduced CPU time, improvement of accuracy, and more compatibility with other SPICE softwares on both Windows and Unix platforms. The proposed design methodology presents how to build static CMOS-like SET circuits, and demonstrates that conventional CMOS circuit design methodologies are all applicable to SET circuit designs based on the methodology. HSPICE simulation results show that, for 1 MΩ junction resistance, the power consumption of a SET NAND2 gate is less than 0.3 pW, and the propagation delay for a SET XOR2 gate is 29.8 ns while driving a 10 aF load.

[1]  Siegfried Selberherr,et al.  SIMON-A simulator for single-electron tunnel devices and circuits , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  A. N. Korotkov,et al.  Room temperature molecular single-electron transistor , 1996 .

[3]  A Paul Alivisatos,et al.  A single-electron transistor made from a cadmium selenide nanocrystal , 1997, Nature.

[4]  J. E. Mooij,et al.  Single-electron inverter , 2000, cond-mat/0011520.

[5]  Yun Seop Yu,et al.  Macromodeling of single-electron transistors for efficient circuit simulation , 1999 .

[6]  Ivar Ekeland.  Mathematics: What you eat is how many you are , 1997, Nature.

[7]  A.M. Ionescu,et al.  A quasi-analytical SET model for few electron circuit simulation , 2002, IEEE Electron Device Letters.

[8]  Bin Yu,et al.  FinFET scaling to 10 nm gate length , 2002, Digest. International Electron Devices Meeting,.

[9]  Byung-Gook Park,et al.  Fabrication of single-electron tunneling transistors with an electrically formed Coulomb island in a silicon-on-insulator nanowire , 2002 .

[10]  Ioannis G. Karafyllidis,et al.  A single-electron XOR gate , 2001 .

[11]  C. Wasshuber.  Computational Single-Electronics , 2001 .

[12]  S. Mahapatra,et al.  Analytical modeling of single electron transistor for hybrid CMOS-SET analog IC design , 2004, IEEE Transactions on Electron Devices.

[13]  S. Leigh,et al.  Probability and Random Processes for Electrical Engineering , 1989 .

[14]  Chaohong Hu,et al.  A single-electron-transistor-based analog/digital converter , 2002, Proceedings of the 2nd IEEE Conference on Nanotechnology.

[15]  Snider,et al.  Digital logic gate using quantum-Dot cellular automata , 1999, Science.

[16]  Phaedon Avouris,et al.  Carbon nanotube field-effect transistors and logic circuits , 2002, DAC '02.

[17]  P. Hadley,et al.  Simulating Hybrid Circuits of Single-Electron Transistors and Field-Effect Transistors , 2003 .

[18]  Konstantin K. Likharev,et al.  Single Electronics: A Correlated Transfer of Single Electrons and Cooper Pairs in Systems of Small Tunnel Junctions , 1991 .

[19]  Atsushi Iwata,et al.  A single-electron stochastic associative processing circuit robust to random background-charge effects and its structure using nanocrystal floating-gate transistors , 2000 .

[20]  W.C.B. Peatman,et al.  Novel resonant tunneling transistor with high transconductance at room temperature , 1994, IEEE Electron Device Letters.

[21]  Kaustav Banerjee,et al.  Few electron devices: towards hybrid CMOS-SET integrated circuits , 2002, DAC '02.

[22]  J. F. Stoddart,et al.  Nanoscale molecular-switch crossbar circuits , 2003 .