Distributed arithmetic based filters for satellite video signals demodulation

The paper proposes a method to use distributed arithmetic (DA) based filters to demodulate video signals on satellites. The demodulator uses a mixer, carrier recovery circuit, symbol recovery circuit and a Root raised cosine filter designed on DA based technique to implement the algorithm. Typical binary digital rates for digitized video are 3-4Mbps. To demodulate such signals, the number of MAC operations required by the filter is more. DA usage eliminates the need of multipliers when implementing MAC. This increases the operational speed and results in high filter throughput. The basic blocks of the demodulator are designed using VHDL and synthesized using Xilinx ISE 10.1.

[1]  K. R. Nataraj,et al.  Development of Algorithm, Architecture and FPGA Implementation of Demodulator for Processing Satellite Data Communication , 2009 .

[2]  . T.Vigneswaran,et al.  Design of Digital FIR Filter Based on Dynamic Distributed Arithmetic Algorithm , 2007 .

[3]  Purna Ramesh Addanki,et al.  FPGA based Design and Implementation of Higher Order FIR Filter using Improved DA Algorithm , 2011 .

[4]  J.E. Mazo,et al.  Digital communications , 1985, Proceedings of the IEEE.

[5]  Timothy Pratt,et al.  Satellite communications , 1986 .

[6]  Pau Closas,et al.  Digital I&Q demodulation in array processing: Theory and implementation , 2008, 2008 16th European Signal Processing Conference.

[7]  M. Kolawole.  Satellite Communication Engineering , 2002 .

[8]  Subhash Kulkarni,et al.  FPGA Implementation of /4 -QPSK Modulator and Demodulator , 2012 .

[9]  K. R. Nataraj,et al.  Development of Algorithm for Demodulator for Processing Satellite Data Communication , 2009 .

[10]  Sandeep Mukthavaram.  Design and FPGA Implementation of an Adaptive Demodulator , 1999 .

[11]  Tang Bin,et al.  Distributed Arithmetic for FIR Filter Design on FPGA , 2007, 2007 International Conference on Communications, Circuits and Systems.

[12]  Venkatesh Krishnan,et al.  An FPGA implementation for a high throughput adaptive filter using distributed arithmetic , 2004, 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines.

[13]  Pal Singh Harjit,et al.  Implementation of High Speed FIR Filter using Serial and Parallel Distributed Arithmetic Algorithm , 2011 .

[14]  J. Pierce.  Satellite Communication. , 1961, Science.

[15]  A. Miri,et al.  Area-Efficient FIR Filter Design on FPGAs using Distributed Arithmetic , 2006, 2006 IEEE International Symposium on Signal Processing and Information Technology.