A mesochronous pipeline scheme for high performance low power digital systems
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[1] S. Tam,et al. Clock generation and distribution for the 130-nm Itanium/sup /spl reg// 2 processor with 6-MB on-die L3 cache , 2004, IEEE Journal of Solid-State Circuits.
[2] W. Liu,et al. Wave-pipelining: a tutorial and research survey , 1998, IEEE Trans. Very Large Scale Integr. Syst..
[3] Yehea I. Ismail,et al. Effects of inductance on the propagation delay and repeater insertion in VLSI circuits , 2000, IEEE Trans. Very Large Scale Integr. Syst..
[4] Wentai Liu,et al. Timing constraints for wave-pipelined systems , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[5] Eby G. Friedman,et al. Clock distribution networks in synchronous digital integrated circuits , 2001, Proc. IEEE.
[6] Alina Deutsch,et al. Designing the best clock distribution network , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).
[7] Ashutosh Das,et al. A new family of semidynamic and dynamic flip-flops with embedded logic for high-performance processors , 1999 .
[8] José G. Delgado-Frias,et al. A Pipelined Multiplier Using A Hybrid Wave-Pipelining Scheme , 2005, CDES.
[9] Thomas A. DeMassa,et al. Digital Integrated Circuits , 1985, 1985 IEEE GaAs IC Symposium Technical Digest.
[10] Narayanan Vijaykrishnan,et al. A clock power model to evaluate impact of architectural and technology optimizations , 2002, IEEE Trans. Very Large Scale Integr. Syst..
[11] J.G. Delgado-Frias,et al. Designing pipelined systems with a clock period approaching pipeline register delay , 2005, 48th Midwest Symposium on Circuits and Systems, 2005..
[12] José G. Delgado-Frias,et al. A mesochronous pipelining scheme for high-performance digital systems , 2006, IEEE Transactions on Circuits and Systems I: Regular Papers.