A simple yet precise capacitance estimation method for on-chip power delivery network towards EMC analysis

[1]  Nasser Masoumi,et al.  Novel methods for accelerating substrate coupling modeling and analysis , 2006, IEICE Electron. Express.

[2]  Patrick Groeneveld.  Going with the flow: bridging the gap between theory and practice in physical design , 2010, ISPD '10.

[3]  Li Chuang Quek,et al.  Characterization of on die capacitance and silicon measurement correlation , 2015, 2015 International Conference on Electronic Packaging and iMAPS All Asia Conference (ICEP-IAAC).

[4]  Masanori Hashimoto,et al.  A Frequency-Dependent Target Impedance Method Fulfilling Both Average and Dynamic Voltage Drop Constraints , 2019, 2019 IEEE 23rd Workshop on Signal and Power Integrity (SPI).

[5]  Jiansheng Xu,et al.  Modeling Mutual Coupling Capacitance Effects of Package RDL to Chip on Radio Frequency ICs , 2018, 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

[6]  Eric Bogatin,et al.  Signal and Power Integrity - Simplified , 2009 .

[7]  A. Waizman,et al.  CPU Power Delivery Impedance Profile Resonances Impact on Core FMAX , 2006, 2006 IEEE Electrical Performane of Electronic Packaging.

[8]  Xiaoping Liu,et al.  The extraction and measurement of on-die impedance for power delivery analysis , 2009, 2009 IEEE 18th Conference on Electrical Performance of Electronic Packaging and Systems.

[9]  Kouji Ichikawa,et al.  Impact of mutual inductance on timing in nano-scale SoC , 2018, IEICE Electron. Express.

[10]  Eby G. Friedman,et al.  Estimation of transient voltage fluctuations in the CMOS-based power distribution networks , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[11]  Yamarita Villavicencio,et al.  EMC-aware design on a microcontroller for automotive applications , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[12]  Andrew B. Kahng,et al.  Improved effective capacitance computations for use in logic and layout optimization , 1999, Proceedings Twelfth International Conference on VLSI Design. (Cat. No.PR00013).

[13]  Atsushi Matsumoto,et al.  Multi-chip NoCs for Automotive Applications , 2012, 2012 IEEE 18th Pacific Rim International Symposium on Dependable Computing.

[14]  R.H. Dennard,et al.  Design Of Ion-implanted MOSFET's with Very Small Physical Dimensions , 1974, Proceedings of the IEEE.

[15]  Narimasa Takahashi,et al.  Analysis of Complete Power-Distribution Network and Co-Design Optimization , 2009 .

[16]  Bok Eng Cheah,et al.  Intrinsic capacitance extraction and estimation for system-on-chip power delivery development , 2012, 2012 IEEE Asia Pacific Conference on Circuits and Systems.

[17]  Masaaki Yamada,et al.  EMI-noise analysis under ASIC design environment , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  Mingming Xu,et al.  Correlation of On-Die capacitance for power delivery network , 2008, 2008 IEEE-EPEP Electrical Performance of Electronic Packaging.

[19]  Toshio Sudo,et al.  Anti-resonance peak shift due to variation of effective package inductance , 2013, 2013 IEEE Electrical Design of Advanced Packaging Systems Symposium (EDAPS).

[20]  Larry D. Smith,et al.  Power distribution system design methodology and capacitor selection for modern CMOS technology , 1999 .

[21]  Manoj Sachdev,et al.  Analysis and Design of On-Chip Decoupling Capacitors , 2013, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[22]  Eby G. Friedman,et al.  On-chip /spl Delta/I noise in the power distribution networks of high speed CMOS integrated circuits , 2000, Proceedings of 13th Annual IEEE International ASIC/SOC Conference (Cat. No.00TH8541).

[23]  Dimitrios Soudris,et al.  VOSsim: A Framework for Enabling Fast Voltage Overscaling Simulation for Approximate Computing Circuits , 2018, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.