Efficient and effective placement for very large circuits

Effective Placement for Very Large Circuits Wern-Jieh Sun and Carl Sechen Department of Electrical Engineering University of Washington Seattle, Washington 98195 We present two major extensions to the implementation of simulated annealing for row-based placement which have enabled it to obtain the best results ever reported for a large set of MCNC benchmark circuits while using the least computation time ever reported for remotely comparable results. Our results indicate that chip area reductions up to 16910 can be expected, compared with TimberWolJSC v6. O. Our new hierarchical annealing-based placement program yields totaG wire length reductions of up to 9% while consuming up to 7.5 times less CPU time in comparison to TimberWoljSC v6. O. In comparison to the Gordian/ Domino program [2][3][4], our new program yields total wire lengths which are always lower (up to 95Zolower) and our program is always faster for circuits with more than 5000 cells (which represents the range of circuit sizes of interest).

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