Hardware Architecture for HOG Feature Extraction

Pedestrian recognition on embedded systems is a challenging problem since accurate recognition requires extensive computation. To achieve real-time pedestrian recognition on embedded systems, we propose hardware architecture suitable for HOG feature extraction, which is a popular method for high-accuracy pedestrian recognition. To reduce computational complexity toward efficient hardware architecture, this paper proposes several methods to simplify the computation of HOG feature extraction, such as conversion of the division, square root, arctangent to more simple operations. To show that such simplifications do not spoil the recognition accuracy, the detection performance is also evaluated using a support vector machine. Moreover, we implement the proposed architecture on an ALTERA Stratix II FPGA using Verilog HDL to evaluate the circuit size and the processing performance of the proposed architecture. Implementation results show that real-time processing for 30 fps VGA video can be achieved if 10 instances of the proposed hardware are used in parallel.