A New Recovery Scheme Against Short-to-Long Duration Transient Faults in Combinational Logic
暂无分享,去创建一个
[1] Arash Reyhani-Masoleh,et al. Parity-Based Fault Detection Architecture of S-box for Advanced Encryption Standard , 2006, 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
[2] David M. Bull,et al. RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance , 2009, IEEE Journal of Solid-State Circuits.
[3] Giorgio Di Natale,et al. A New Bulk Built-In Current Sensor-Based Strategy for Dealing with Long-Duration Transient Faults in Deep-Submicron Technologies , 2011, 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems.
[4] Christos A. Papachristou,et al. An efficient BICS design for SEUs detection and correction in semiconductor memories , 2005, Design, Automation and Test in Europe.
[5] Luigi Carro,et al. System Level Approaches for Mitigation of Long Duration Transient Faults in Future Technologies , 2007, 12th IEEE European Test Symposium (ETS'07).
[6] Mehdi Baradaran Tahoori,et al. Transient Error Detection and Recovery in Processor Pipelines , 2009, 2009 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
[7] R. Koch,et al. Towards a Flexible Fault-Tolerant System-on-Chip , 2009 .
[8] B. Rouzeyre,et al. Timing issues for an efficient use of concurrent error detection codes , 2011, 2011 12th Latin American Test Workshop (LATW).
[9] Cecilia Metra,et al. Transient Fault and Soft Error On-die Monitoring Scheme , 2010, 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems.
[10] Michael Nicolaidis. Time redundancy based soft-error tolerance to rescue nanometer technologies , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).
[11] Fernanda Gusmão de Lima Kastensmidt,et al. Using Bulk Built-in Current Sensors to Detect Soft Errors , 2006, IEEE Micro.
[12] Pierre Dusart,et al. Differential Fault Analysis on A.E.S , 2003, ACNS.
[13] David Blaauw,et al. Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation , 2003, MICRO.
[14] Sung-Ming Yen,et al. Differential Fault Analysis on AES Key Schedule and Some Coutnermeasures , 2003, ACISP.
[15] Lorena Anghel,et al. Cost reduction and evaluation of temporary faults detecting technique , 2000, DATE '00.
[16] Bruno Rouzeyre,et al. How to sample results of concurrent error detection schemes in transient fault scenarios? , 2011, 2011 12th European Conference on Radiation and Its Effects on Components and Systems.
[17] Luigi Carro,et al. XOR-Based Low Cost Checkers for Combinational Logic , 2008, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems.
[18] Eltayeb Salih Abuelyaman,et al. Differential Fault Analysis , 2005, International Conference on Internet Computing.
[19] Mikko H. Lipasti,et al. Time redundant parity for low-cost transient error detection , 2011, 2011 Design, Automation & Test in Europe.
[20] Edward J. McCluskey,et al. Which concurrent error detection scheme to choose ? , 2000, Proceedings International Test Conference 2000 (IEEE Cat. No.00CH37159).
[21] K.A. Bowman,et al. Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance , 2009, IEEE Journal of Solid-State Circuits.
[22] Luigi Carro,et al. Using built-in sensors to cope with long duration transient faults in future technologies , 2007, 2007 IEEE International Test Conference.