A Self-Aligned Ni-InGaAs Contact Technology for InGaAs Channel n-MOSFETs

[1]  Masanori Murakami,et al.  Development of refractory ohmic contact materials for gallium arsenide compound semiconductors , 2002 .

[2]  Xiao Gong,et al.  Self-Aligned Gate-First In0.7Ga0.3As n-MOSFETs with an InP Capping Layer for Performance Enhancement , 2011 .

[3]  Peide D. Ye,et al.  Effects of (NH4)2S passivation on the off-state performance of 3-dimensional InGaAs metal-oxide-semiconductor field-effect transistors , 2011 .

[4]  M. Radosavljevic,et al.  Study of the inversion behaviors of Al2O3/InxGa1−xAs metal–oxide–semiconductor capacitors with different In contents , 2010 .

[5]  M. Rodwell,et al.  $\hbox{In}_{0.53}\hbox{Ga}_{0.47}\hbox{As}$ Channel MOSFETs With Self-Aligned InAs Source/Drain Formed by MEE Regrowth , 2009, IEEE Electron Device Letters.

[6]  H.C. Lin,et al.  Submicrometer Inversion-Type Enhancement-Mode InGaAs MOSFET With Atomic-Layer-Deposited $\hbox{Al}_{2}\hbox{O}_{3}$ as Gate Dielectric , 2007, IEEE Electron Device Letters.

[7]  R. M. Swanson,et al.  Modeling and measurement of contact resistances , 1987, IEEE Transactions on Electron Devices.

[8]  Xiao Gong,et al.  In0.7Ga0.3As Channel n-MOSFET with Self-Aligned Ni–InGaAs Source and Drain , 2011 .

[9]  P. Ye,et al.  High-Performance Inversion-Type Enhancement-Mode InGaAs MOSFET With Maximum Drain Current Exceeding 1 A/mm , 2008, IEEE Electron Device Letters.

[10]  Mark J. W. Rodwell,et al.  InGaAs channel MOSFET with self-aligned source/drain MBE regrowth technology , 2009 .

[11]  J. Bucchignano,et al.  High-Performance $\hbox{In}_{0.7}\hbox{Ga}_{0.3}\hbox{As}$ -Channel MOSFETs With High-$\kappa$ Gate Dielectrics and $\alpha$-Si Passivation , 2009, IEEE Electron Device Letters.

[12]  Mark J. W. Rodwell,et al.  Ultralow resistance in situ Ohmic contacts to InGaAs/InP , 2008 .

[13]  R. Chau,et al.  Benchmarking nanotechnology for high-performance and low-power logic transistor applications , 2004, IEEE Transactions on Nanotechnology.

[14]  Ivana,et al.  Source/Drain Engineering for In0.7Ga0.3As N-Channel Metal–Oxide–Semiconductor Field-Effect Transistors: Raised Source/Drain with In situ Doping for Series Resistance Reduction , 2011 .

[15]  K. Saraswat,et al.  Metal/III-V effective barrier height tuning using atomic layer deposition of high-κ/high-κ bilayer interfaces , 2011 .

[16]  Wilman Tsai,et al.  High-performance self-aligned inversion-channel In0.53Ga0.47As metal-oxide-semiconductor field-effect-transistor with Al2O3∕Ga2O3(Gd2O3) as gate dielectrics , 2008 .

[17]  Ivana,et al.  Selective Wet Etching Process for Ni-InGaAs Contact Formation in InGaAs N-MOSFETs with Self-Aligned Source and Drain , 2011 .

[18]  Suman Datta,et al.  III-V field-effect transistors for low power digital logic applications , 2007 .

[19]  M. Holland,et al.  Fully self-aligned process for fabricating 100nm gate length enhancement mode GaAs metal-oxide-semiconductor field-effect transistors , 2009 .

[20]  Jack C. Lee,et al.  Self-aligned n-channel metal-oxide-semiconductor field effect transistor on high-indium-content In0.53Ga0.47As and InP using physical vapor deposition HfO2 and silicon interface passivation layer , 2008 .

[21]  Experimental demonstration of In0.53Ga0.47As field effect transistors with scalable nonalloyed source/drain contacts , 2011 .

[22]  S. Datta,et al.  Ultrahigh-Speed 0.5 V Supply Voltage $\hbox{In}_{0.7} \hbox{Ga}_{0.3}\hbox{As}$ Quantum-Well Transistors on Silicon Substrate , 2007, IEEE Electron Device Letters.

[23]  Yasuyuki Miyamoto,et al.  InP/InGaAs Composite Metal–Oxide–Semiconductor Field-Effect Transistors with Regrown Source and Al2O3 Gate Dielectric Exhibiting Maximum Drain Current Exceeding 1.3 mA/µm , 2011 .

[24]  M. Heyns,et al.  Ultimate Scaling of CMOS Logic Devices with Ge and III–V Materials , 2009 .

[25]  Suman Datta,et al.  Investigation of scalability of In0.7Ga0.3As quantum well field effect transistor (QWFET) architecture for logic applications , 2011 .

[26]  Y. Nishi,et al.  Atomic Layer Deposition of Dielectrics on Ge and III–V Materials for Ultrahigh Performance Transistors , 2009 .

[27]  Jack C. Lee,et al.  High performance In0.7Ga0.3As metal-oxide-semiconductor transistors with mobility >4400 cm2/V s using InP barrier layer , 2009 .

[28]  Ivana,et al.  Reduction of Off-State Leakage Current in In0.7Ga0.3As Channel n-MOSFETs with Self-Aligned Ni-InGaAs Contact Metallization , 2011 .

[29]  Jack C. Lee,et al.  InAs inserted InGaAs buried channel metal-oxide-semiconductor field-effect-transistors with atomic-layer-deposited gate dielectric , 2011 .

[30]  A. Dimoulas,et al.  Source and Drain Contacts for Germanium and III–V FETs for Digital Logic , 2009 .

[31]  Y. Yeo,et al.  Lattice-Mismatched $\hbox{In}_{0.4}\hbox{Ga}_{0.6} \hbox{As}$ Source/Drain Stressors With In Situ Doping for Strained $\hbox{In}_{0.53}\hbox{Ga}_{0.47}\hbox{As}$ Channel n-MOSFETs , 2009, IEEE Electron Device Letters.

[32]  H. H. Berger,et al.  Contact Resistance and Contact Resistivity , 1972 .