Comparison between isolated SCR & embedded dual isolated SCR power devices for ESD power clamp in C45nm CMOS technology
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P. Galy | J. Bourgeat | A. Dray | B. Jacquier | J. Jimenez | C. Entringer
[1] Zhiwei Liu,et al. An Improved Bidirectional SCR Structure for Low-Triggering ESD Protection Applications , 2008, IEEE Electron Device Letters.
[2] Philippe Galy,et al. Local ESD protection structure based on silicon controlled rectifier achieving very low overshoot voltage , 2009, 2009 31st EOS/ESD Symposium.
[3] H. Grubin. The physics of semiconductor devices , 1979, IEEE Journal of Quantum Electronics.
[4] S. M. Sze,et al. Physics of semiconductor devices , 1969 .
[5] Zhiwei Liu,et al. Novel Silicon-Controlled Rectifier (SCR) for High-Voltage Electrostatic Discharge (ESD) Applications , 2008, IEEE Electron Device Letters.
[6] E. Rosenbaum,et al. A dual-base triggered SCR with very low leakage current and adjustable trigger voltage , 2008, EOS/ESD 2008 - 2008 30th Electrical Overstress/Electrostatic Discharge Symposium.
[7] Ming-Dou Ker,et al. SCR device with dynamic holding voltage for on-chip ESD protection in a 0.25-/spl mu/m fully salicided CMOS process , 2004 .
[8] H. Gieser,et al. Transient induced latch-up triggered by very fast pulses , 1999 .
[9] Ming-Dou Ker,et al. Design optimization of ESD protection and latchup prevention for a serial I/O IC , 2004, Microelectron. Reliab..
[10] Kwang-Yeob Lee,et al. Design of SCR-based ESD protection device for power clamp using deep-submicron CMOS technology , 2009, Microelectron. J..
[11] Junjun Li,et al. Investigation of voltage overshoots in diode triggered silicon controlled rectifiers (DTSCRs) under very fast transmission line pulsing (VFTLP) , 2009, 2009 31st EOS/ESD Symposium.
[12] Ming-Dou Ker,et al. Transient-Induced Latchup Dependence on Power-Pin Damping Frequency and Damping Factor in CMOS Integrated Circuits , 2007, IEEE Transactions on Electron Devices.
[13] Yu Bo,et al. A novel dual SCR device for ESD protection , 2009, 2009 IEEE 8th International Conference on ASIC.
[14] Ming-Dou Ker,et al. Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale CMOS Technology , 2009, IEEE J. Solid State Circuits.
[15] Koen G. Verhaege,et al. High Holding Current SCRs (HHI-SCR) for ESD protection and latch-up immune IC operation , 2002, 2002 Electrical Overstress/Electrostatic Discharge Symposium.