HIPDN: A POWER DISTRIBUTION NETWORK FOR EFFICIENT ON -CHIP POWER DELIVERY AND FINE - GRAIN LOW -POWER APPLICATIONS

While the semiconductor roadmap is about to locate in 16nm-FinFET (or Tri-Gate) era, power budget is being entitled major concern to contemporary electronics and future nanometer devices. In this work, a new Power Distribution Network (PDN), referred to as HiPDN, is disclosed for further fine-grain power saving and higher power integrity for supplies in multi-voltage domains. The proposed PDN employs two types of Integrated Voltage Regulators (IVR) with large difference in voltage regulation range. By combining the proposed PDN with the Adaptive Voltage Scaling (AVS) technique, voltage guard-bands can be mitigated to lower the safety margin for voltage variation, i.e., reducing DC set points, thereby effectively decreasing the overhead of power dissipation. In comparison to existing PDNs, theoretical results with a simple equivalent circuit model demonstrate an increase of power saving achieved by HiPDN, thus, allowing longer battery life. Finally, this work provides an on-chip power delivery methodology to improve power efficiency and a simple model to evaluate a PDN and its IVRs.

[1]  Robert C. Aitken,et al.  Low Power Methodology Manual - for System-on-Chip Design , 2007 .

[2]  Jan M. Rabaey,et al.  Ultralow-Power Design in Near-Threshold Region , 2010, Proceedings of the IEEE.

[3]  Peng Li,et al.  A 0.38 V near/sub-VT digitally controlled low-dropout regulator with enhanced power supply noise rejection in 90 nm CMOS process , 2013, IET Circuits Devices Syst..

[4]  Wei Chen,et al.  5.4 Ivytown: A 22nm 15-core enterprise Xeon® processor family , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[5]  Martin Wirnshofer.  Variation-Aware Adaptive Voltage Scaling for Digital CMOS Circuits , 2013 .

[6]  Ting Yu,et al.  Efficient simulation-based optimization of power grid with on-chip voltage regulator , 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).

[7]  Dragan Maksimovic,et al.  Closed-loop adaptive voltage scaling controller for standard-cell ASICs , 2002, ISLPED '02.

[8]  Robert H. Dennard,et al.  Practical Strategies for Power-Efficient Computing Technologies , 2010, Proceedings of the IEEE.

[9]  Sung Kyu Lim,et al.  Thermal analysis and optimization of 2.5-D integrated voltage regulator , 2012, 2012 IEEE 21st Conference on Electrical Performance of Electronic Packaging and Systems.

[10]  Josep Torrellas,et al.  Coping with Parametric Variation at Near-Threshold Voltages , 2013, IEEE Micro.

[11]  Nam Sung Kim,et al.  Cost-effective power delivery to support per-core voltage domains for power-constrained processors , 2012, DAC Design Automation Conference 2012.

[12]  Jonathan White,et al.  5.5 Steamroller: An x86-64 core implemented in 28nm bulk CMOS , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[13]  Luca P. Carloni,et al.  A Switched-Inductor Integrated Voltage Regulator With Nonlinear Feedback and Network-on-Chip Load in 45 nm SOI , 2012, IEEE Journal of Solid-State Circuits.

[14]  Johann W. Kolar,et al.  4.7 A sub-ns response on-chip switched-capacitor DC-DC voltage regulator delivering 3.7W/mm2 at 90% efficiency using deep-trench capacitors in 32nm SOI CMOS , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[15]  Wilfred Gomes,et al.  5.9 Haswell: A family of IA 22nm processors , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[16]  R.H. Dennard,et al.  Design Of Ion-implanted MOSFET's with Very Small Physical Dimensions , 1974, Proceedings of the IEEE.

[17]  Selcuk Kose.  Thermal Implications of On-Chip Voltage Regulation: Upcoming Challenges and Possible Solutions , 2014, DAC 2014.

[18]  David Blaauw,et al.  Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits , 2010, Proceedings of the IEEE.

[19]  Kevin G. Stawiasz,et al.  5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8TM microprocessor , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[20]  Selcuk Kose,et al.  Regulator-gating: adaptive management of on-chip voltage regulators , 2014, GLSVLSI 2014.

[21]  Christopher Gonzalez,et al.  5.1 POWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[22]  David Flynn.  An ARM perspective on addressing low-power energy-efficient SoC designs , 2012, ISLPED '12.

[23]  Michael Bedford Taylor,et al.  Is dark silicon useful? Harnessing the four horsemen of the coming dark silicon apocalypse , 2012, DAC Design Automation Conference 2012.

[24]  Abraham Pressman,et al.  Switching Power Supply Design , 1997 .

[25]  Peng Li,et al.  Stability assurance and design optimization of large power delivery networks with multiple on-chip voltage regulators , 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[26]  Takayasu Sakurai,et al.  Analog-Assisted Digital Low Dropout Regulator (AAD-LDO) with 59% Faster Transient Response and 28% Ripple Reduction , 2013 .

[27]  Pingqiang Zhou,et al.  Exploration of on-chip switched-capacitor DC-DC converter for multicore processors using a distributed power delivery network , 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

[28]  Eby G. Friedman,et al.  Heterogeneous Methodology for Energy Efficient Distribution of On-Chip Power Supplies , 2013, IEEE Transactions on Power Electronics.