Delay and Power Expressions for a CMOS Inverter Driving a Resistive-Capacitive Load

A delay and power model of a CMOS inverter driving aresistive-capacitive load is presented. The model is derivedfrom Sakurai‘s alpha-power law and exhibits good accuracy. Themodel can be used to design and analyze those CMOS invertersthat drive a large RC load when considering bothspeed and power. Expressions are provided for estimating thepropagation delay and transition time which exhibit less than27% discrepancy from SPICE for a wide variety of RCloads. Expressions are also provided for modeling the short-circuitpower dissipation of a CMOS inverter driving a resistive-capacitiveinterconnect line which are accurate to within 15% of SPICEfor most practical loads.

[1]  Mark A. Franklin,et al.  Optimum buffer circuits for driving long uniform lines , 1991 .

[2]  J.D. Meindl,et al.  Optimal interconnection circuits for VLSI , 1985, IEEE Transactions on Electron Devices.

[3]  S. Bothra,et al.  Analysis of the effects of scaling on interconnect delay in ULSI circuits , 1993 .

[4]  Karem A. Sakallah,et al.  Analytical transient response of CMOS inverters , 1992 .

[5]  Hidetoshi Onodera,et al.  Estimation of short-circuit power dissipation and its influence on propagation delay for static CMOS gates , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[6]  H. Shichman,et al.  Modeling and simulation of insulated-gate field-effect transistor switching circuits , 1968 .

[7]  R. J. Antinone,et al.  The modeling of resistive interconnects for integrated circuits , 1983 .

[8]  Kjell O. Jeppson,et al.  CMOS Circuit Speed and Buffer Optimization , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[9]  Yvon Savaria,et al.  Optimal methods of driving interconnections in VLSI circuits , 1992, [Proceedings] 1992 IEEE International Symposium on Circuits and Systems.

[10]  Jason Cong,et al.  Simultaneous Driver And Wire Sizing For Performance And Power Optimization* , 1994, IEEE/ACM International Conference on Computer-Aided Design.

[11]  A. R. Newton,et al.  Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas , 1990 .

[12]  Srinivasa Vemuru,et al.  Short-circuit power dissipation estimation for cmos logic gates , 1994 .

[13]  M.-C. Shiau,et al.  Delay models and speed improvement techniques for RC tree interconnections among small-geometry CMOS inverters , 1990 .

[14]  V. Adler,et al.  Delay and Power Expressions for a CMOS Inverter Driving a Resistive-Capacitive Load , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[15]  Sung-Mo Kang,et al.  Statistical estimation of short-circuit power in VLSI circuits , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[16]  Hidetoshi Onodera,et al.  Estimation of short-Circuit Power Dissipation for Static CMOS Gates , 1996 .

[17]  Jason Cong,et al.  Simultaneous driver and wire sizing for performance and power optimization , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[18]  Spiridon Nikolaidis,et al.  Modeling the CMOS short-circuit power dissipation , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.

[19]  Hendrikus J. M. Veendrick,et al.  Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits , 1984 .