Research on VLSI test compression
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[1] Nur A. Touba,et al. Survey of Test Vector Compression Techniques , 2006, IEEE Design & Test of Computers.
[2] Kedarnath J. Balakrishnan,et al. XWRC: externally-loaded weighted random pattern testing for input test data compression , 2005, IEEE International Conference on Test, 2005..
[3] Youhua Shi,et al. FCSCAN: an efficient multiscan-based test compression technique for test cost reduction , 2006, Asia and South Pacific Conference on Design Automation, 2006..
[4] Aiman H. El-Maleh. A hybrid test compression technique for efficient testing of systems-on-a-chip , 2003, 10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003.
[5] Nur A. Touba,et al. Scan vector compression/decompression using statistical coding , 1999, Proceedings 17th IEEE VLSI Test Symposium (Cat. No.PR00146).
[6] Kedarnath J. Balakrishnan,et al. PIDISC: pattern independent design independent seed compression technique , 2006, 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06).
[7] Kozo Kinoshita,et al. Reducing scan shifts using folding scan trees , 2003, 2003 Test Symposium.
[8] Alex Orailoglu,et al. Test volume and application time reduction through scan chain concealment , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).
[9] Terumine Hayashi,et al. On Test Data Compression Using Selective Don’t-Care Identification , 2005, Journal of Computer Science and Technology.
[10] Subhasish Mitra,et al. X-compact: an efficient response compaction technique , 2004, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.