论文信息 - A digitally self-calibrating 14-bit 10-MHz CMOS pipelined A/D converter

A digitally self-calibrating 14-bit 10-MHz CMOS pipelined A/D converter

A digitally self-calibrating pipelined analog-to-digital converter (ADC) featuring 1.5-bit/stage structure is presented. The integral (INL) and differential nonlinearity (DNL) errors are removed using a novel digital calibration algorithm, which also eliminates missing codes that can occur with other calibration algorithms near the extremes of the input range. After calibration, the measured DNL is /spl plusmn/0.6 LSB and the INL is /spl plusmn/2.5 LSB at the 14-bit level. Sampling at a 10-MHz rate, the chip dissipates 220 mW and (post-calibration) yields a signal-to-noise ratio of 77 dB and a spurious-free dynamic range of 95 dB with 4.8-MHz sine wave input signal. The chip is fabricated in 0.5-/spl mu/m CMOS double-poly double-metal process, measures 3.8 mm /spl times/ 3.3 mm (150 mil /spl times/ 130 mil), and operates from a single 5-V supply.

T. L. Sculley | S.-Y. Chuang

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