Evolutionary Algorithms in Unreliable Memory

Guaranteeing the underlying reliability of computer memory is becoming more difficult as chip dimensions scale down, and as power limitations make lower voltages desirable. To date, the reliability of memory has been seen as the responsibility of the computer engineer, any underlying unreliability being hidden from programmers. However it may make sense, in future, to shift this balance, optionally exposing the unreliability to programmers, permitting them to choose between higher and lower reliabilities. This is particularly relevant to the data-intensive applications which might potentially provide the "killer apps" for anticipated future many-core architectures. We simulated the effect of unreliable memory on the behaviour of a slightly re-programmed variant of a typical Genetic Algorithm (GA) on a range of optimisation problems. With only minor change to the code, most variables held in unreliable memory, and error rates up to 10^-3, the memory unreliability had no real effect on the GA behaviour. For higher error rates, the effects became noticeable, and the behaviour of the GA was unacceptable once the error rate reached 10^-2.

[1]  Richard W. Hamming,et al.  Error detecting and error correcting codes , 1950 .

[2]  J. von Neumann,et al.  Probabilistic Logic and the Synthesis of Reliable Organisms from Unreliable Components , 1956 .

[3]  K. Dejong,et al.  An analysis of the behavior of a class of genetic adaptive systems , 1975 .

[4]  Kenneth Alan De Jong,et al.  An analysis of the behavior of a class of genetic adaptive systems. , 1975 .

[5]  S. Ulam,et al.  Adventures of a Mathematician , 2019, Mathematics: People · Problems · Results.

[6]  Joel H. Spencer,et al.  Coping with Errors in Binary Search Procedures , 1980, J. Comput. Syst. Sci..

[7]  Andrew Chi-Chih Yao,et al.  On Fault-Tolerant Networks for Sorting , 1985, SIAM J. Comput..

[8]  Allan Gottlieb,et al.  Highly parallel computing , 1989, Benjamin/Cummings Series in computer science and engineering.

[9]  A. E. Eiben,et al.  Global Convergence of Genetic Algorithms: A Markov Chain Analysis , 1990, PPSN.

[10]  A. E. Eiben,et al.  Global conver-gence of genetic algorithms: an infinite Markov chain analysis , 1991 .

[11]  Piotr Indyk,et al.  Shared-Memory Simulations on a Faulty-Memory DMM , 1996, ICALP.

[12]  Piotr Indyk,et al.  On Word-Level Parallelism in Fault-Tolerant Computing , 1996, STACS.

[13]  Xin Yao,et al.  Evolutionary programming made faster , 1999, IEEE Trans. Evol. Comput..

[14]  Adrian Stoica,et al.  Fault-tolerant evolvable hardware using field-programmable transistor arrays , 2000, IEEE Trans. Reliab..

[15]  Andrew M. Tyrrell,et al.  Evolutionary strategies and intrinsic fault tolerance , 2001, Proceedings Third NASA/DoD Workshop on Evolvable Hardware. EH-2001.

[16]  Adrian Stoica,et al.  Evolvable hardware solutions for extreme temperature electronics , 2001, Proceedings Third NASA/DoD Workshop on Evolvable Hardware. EH-2001.

[17]  Colin R. Reeves,et al.  Genetic Algorithms: Principles and Perspectives: A Guide to Ga Theory , 2002 .

[18]  Andrzej Pelc,et al.  Searching games with errors - fifty years of coping with liars , 2002, Theor. Comput. Sci..

[19]  A. Hamilton-Wright,et al.  Fault-tolerant network computation of individuals in genetic algorithms , 2002, Proceedings of the 2002 Congress on Evolutionary Computation. CEC'02 (Cat. No.02TH8600).

[20]  Leonid Oliker,et al.  Scientific Computations on Modern Parallel Vector Systems , 2004, Proceedings of the ACM/IEEE SC2004 Conference.

[21]  Larry C. Andrews Bit Error Rate , 2004 .

[22]  Joseph A. Catania Soft errors in electronic memory-a white paper , 2004 .

[23]  T. Schloesser,et al.  Challenges for the DRAM cell scaling to 40nm , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[24]  M.A. Alam,et al.  Scaling Limits of Capacitorless Double Gate DRAM Cell , 2006, 2006 International Conference on Simulation of Semiconductor Processes and Devices.

[25]  Francisco Fernández de Vega,et al.  A Fault Tolerant Optimization Algorithm based on Evolutionary Computation , 2006, 2006 International Conference on Dependability of Computer Systems.

[26]  Fabrizio Grandoni,et al.  Optimal resilient sorting and searching in the presence of memory faults , 2006, Theor. Comput. Sci..

[27]  Arvind Kumar,et al.  Silicon CMOS devices beyond scaling , 2006, IBM J. Res. Dev..

[28]  Fabrizio Grandoni,et al.  Optimal resilient sorting and searching in the presence of memory faults , 2006 .

[29]  Giuseppe F. Italiano,et al.  Sorting and Searching in Faulty Memories , 2008, Algorithmica.

[30]  Philip Ross,et al.  Why CPU Frequency Stalled , 2008, IEEE Spectrum.

[31]  J. Kessenich,et al.  Bit error rate in NAND Flash memories , 2008, 2008 IEEE International Reliability Physics Symposium.

[32]  Stephen R. Marsland,et al.  Convergence Properties of (μ + λ) Evolutionary Algorithms , 2011, AAAI.