Overlay metrology for low-k1: challenges and solutions

Typical overlay metrology marks like Box-in-Box or Advanced-Imaging-Marks print surprisingly poor when exposed with extreme off-axis-illumination. This paper analyzes the root-cause for this behavior and establishes a method how to understand and predict the results of overlay metrology on resist. A simulation flow is presented which covers the lithographic exposure as well as the actual inspection of the resist profiles. This flow is then used to study the impact of scanner/process imperfections on the overlay measurements; both image-based and diffraction-based overlay metrology are covered. This helps to gain a deeper understanding of the critical parameters in the printing and inspection of overlay marks, and eventually develop and assess mark enhancement strategies for image-based overlay metrology such as chopping, or assess the benefit of diffraction-based overlay metrology. In parallel to the simulations, results of wafer exposures are presented which investigate various aspects of overlay metrology and validate our simulations.