Fast heuristic and exact algorithms for two-level hazard-free logic minimization

None of the available minimizers for two-level hazard-free logic minimization can synthesize very large circuits. This limitation has forced researchers to resort to manual and automated circuit partitioning techniques. This paper introduces two new two-level hazard-free logic minimizers: ESPRESSO-HF, a heuristic method loosely based on ESPRESSO-II, and IMPYMIN, an exact method based on implicit data structures. Both minimizers can solve all currently available examples, which range up to 32 inputs and 33 outputs. These include examples that have never been solved before. For the more difficult examples that can be solved by other minimizers, our methods are several orders of magnitude faster. As by-products of these algorithms, we also present two additional results. First, we propose a fast new method to check if a hazard-free covering problem can feasibly be solved. Second, we introduce a novel reformulation of the two-level hazard-free logic minimization problem by capturing hazard-freedom constraints within a synchronous function through the addition of new variables.

[1]  J.W.J.M. Rutten,et al.  A divide and conquer strategy for hazard free 2-level logic synthesis , 1997 .

[2]  Luciano Lavagno,et al.  Algorithms for Synthesis and Testing of Asynchronous Circuits , 1993 .

[3]  Paul I. Pénzes,et al.  The design of an asynchronous MIPS R3000 microprocessor , 1997, Proceedings Seventeenth Conference on Advanced Research in VLSI.

[4]  Olivier Coudert,et al.  Two-level logic minimization: an overview , 1994, Integr..

[5]  Hugo De Man,et al.  Assassin: a synthesis system for asynchronous control circuits , 1994 .

[6]  Steven M. Nowick,et al.  UCLOCK: automated design of high-performance unclocked state machines , 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[7]  CoudertOlivier Two-level logic minimization: an overview , 1994 .

[8]  David L. Dill,et al.  Exact two-level minimization of hazard-free logic with multiple-input changes , 1992, ICCAD.

[9]  Shin-ichi Minato,et al.  Zero-Suppressed BDDs for Set Manipulation in Combinatorial Problems , 1993, 30th ACM/IEEE Design Automation Conference.

[10]  Tsutomu Sasao An application of multiple-valued logic to a design of programmable logic arrays , 1978, MVL '78.

[11]  Mark E. Dean,et al.  The design of a high-performance cache controller: a case study in asynchronous synthesis , 1993, Integr..

[12]  Kenneth Y. Yun,et al.  Synthesis of 3D asynchronous state machines , 1992, Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computers & Processors.

[13]  Ivan E. Sutherland,et al.  Counter ow Pipeline Processor Architecture , 1994 .

[14]  Robert K. Brayton,et al.  Optimal State Assignment for Finite State Machines , 1985, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[15]  Ken Stevens,et al.  Automatic Synthesis of Fast Compact Asynchronous Control Circuits , 1993, Asynchronous Design Methodologies.

[16]  Ivan E. Sutherland,et al.  The counterflow pipeline processor architecture , 1994, IEEE Design & Test of Computers.

[17]  Olivier Coudert,et al.  On solving covering problems , 1996, DAC '96.

[18]  Alan Marshall,et al.  Designing an asynchronous communications chip , 1994, IEEE Design & Test of Computers.

[19]  Tao Wu,et al.  Espresso-HF: a heuristic hazard-free minimizer for two-level logic , 1996, DAC '96.

[20]  Andrew Wolfe,et al.  A fast asynchronous Huffman decoder for compressed-code embedded processors , 1998, Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems.

[21]  Takashi Nanya,et al.  TITAC: design of a quasi-delay-insensitive microprocessor , 1994, IEEE Design & Test of Computers.

[22]  Niraj K. Jha,et al.  Synthesis of asynchronous circuits for stuck-at and robust path delay fault testability , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[23]  Olivier Coudert,et al.  New Ideas for Solving Covering Problems , 1995, 32nd Design Automation Conference.

[24]  Marly Roncken,et al.  Asynchronous circuits for low power: a DCC error corrector , 1994, IEEE Design & Test of Computers.

[25]  Tam-Anh Chu,et al.  Synthesis of self-timed VLSI circuits from graph-theoretic specifications , 1987 .

[26]  Steven M. Nowick,et al.  An implicit method for hazard-free two-level logic minimization , 1998, Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems.

[27]  Olivier Coudert,et al.  Doing two-level logic minimization 100 times faster , 1995, SODA '95.

[28]  David L. Dill,et al.  Synthesis of asynchronous state machines using a local clock , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[29]  David L. Dill,et al.  Exact two-level minimization of hazard-free logic with multiple-input changes , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[30]  Polly Siegel,et al.  The Design ofAn Asynchronous Communications Chip , 1994 .

[31]  Steven M. Nowick,et al.  Synthesis of low-power asynchronous circuits in a specified environment , 1997, Proceedings of 1997 International Symposium on Low Power Electronics and Design.

[32]  Luciano Lavagno,et al.  Petrify: A Tool for Manipulating Concurrent Specifications and Synthesis of Asynchronous Controllers (Special Issue on Asynchronous Circuit and System Design) , 1997 .

[33]  Stephen H. Unger,et al.  Asynchronous sequential switching circuits , 1969 .

[34]  Peter A. Beerel CAD tools for the synthesis, verification, and testability of robust asynchronous circuits , 1995 .

[35]  L. S. Nielsen,et al.  A low-power asynchronous data-path for a FIR filter bank , 1996, Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems.

[36]  Ganesh Gopalakrishnan,et al.  A technique for synthesizing distributed burst-mode circuits , 1996, DAC '96.

[37]  Peter A. Beerel,et al.  The design and verification of a high-performance low-control-overhead asynchronous differential equation solver , 1997, Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems.

[38]  Kenneth Y. Yun,et al.  A high-performance asynchronous SCSI controller , 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.

[39]  Michael Kishinevsky,et al.  Concurrent hardware : the theory and practice of self-timed design , 1993 .

[40]  Michel R. C. M. Berkelaar,et al.  Improved state assignment for burst mode finite state machines , 1997, Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems.

[41]  Andrew Wolfe,et al.  A high-speed asynchronous decompression circuit for embedded processors , 1997, Proceedings Seventeenth Conference on Advanced Research in VLSI.

[42]  Steven M. Burns,et al.  The design of an asynchronous microprocessor , 1989, CARN.

[43]  Steven M. Nowick,et al.  An introduction to asynchronous circuit design , 1998 .

[44]  Alberto L. Sangiovanni-Vincentelli,et al.  Multiple-Valued Minimization for PLA Optimization , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[45]  Joep L. W. Kessels,et al.  Designing asynchronous standby circuits for a low-power pager , 1997, Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems.

[46]  Jim D. Garside,et al.  AMULET2e: an asynchronous embedded controller , 1997, Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems.

[47]  Bill Lin,et al.  Symbolic hazard-free minimization and encoding of asynchronous finite state machines , 1995, ICCAD.

[48]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[49]  Luciano Lavagno,et al.  Complete state encoding based on the theory of regions , 1996, Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems.

[50]  C. A. J. van Eijk,et al.  An efficient divide and conquer algorithm for exact hazard free logic minimization , 1998, Proceedings Design, Automation and Test in Europe.