Design for the discrete cosine transform in VLSI

The discrete cosine transform is reviewed with the aid of recent implementations of the 8/spl times/8 transform. The distinct roles of algorithmic and multiplier design are identified, and key circuit and logic innovations are highlighted.

[1]  Gregory K. Wallace,et al.  The JPEG still picture compression standard , 1991, CACM.

[2]  Chin-Liang Wang,et al.  New systolic array implementation of the 2-D discrete cosine transform and its inverse , 1995, IEEE Trans. Circuits Syst. Video Technol..

[3]  Didier Le Gall,et al.  MPEG: a video compression standard for multimedia applications , 1991, CACM.

[4]  Jar-Ferr Yang,et al.  VLSI implementation of parallel coefficient-by-coefficient two-dimensional IDCT processor , 1995, IEEE Trans. Circuits Syst. Video Technol..

[5]  Wen-Hsiung Chen,et al.  A Fast Computational Algorithm for the Discrete Cosine Transform , 1977, IEEE Trans. Commun..

[6]  Nagarajan Ranganathan,et al.  JAGUAR: a fully pipelined VLSI architecture for JPEG image compression standard , 1995, Proc. IEEE.

[7]  Masahiko Yoshimoto,et al.  A 100-MHz 2-D discrete cosine transform core processor , 1992 .

[8]  K. J. Ray Liu,et al.  Unified parallel lattice structures for time-recursive discrete cosine/sine/Hartley transforms , 1993, IEEE Trans. Signal Process..

[9]  K. J. Ray Liu,et al.  Full custom VLSI implementation of high-speed 2-D DCT/IDCT chip , 1994, Proceedings of 1st International Conference on Image Processing.

[10]  Jinn-Nang Kao,et al.  A 0.8 /spl mu/ 100-MHz 2-D DCT core processor , 1994 .

[11]  K. J. Ray Liu,et al.  Real-time parallel and fully pipelined two-dimensional DCT lattice structures with application to HDTV systems , 1992, IEEE Trans. Circuits Syst. Video Technol..

[12]  Takao Onoye,et al.  VLSI implementation of inverse discrete cosine transformer and motion compensator for MPEG2 HDTV video decoding , 1995, IEEE Trans. Circuits Syst. Video Technol..

[13]  C.A.T. Salama,et al.  CMOS differential pass-transistor logic design , 1987 .

[14]  Y. Arai,et al.  A Fast DCT-SQ Scheme for Images , 1988 .

[15]  William H. Press,et al.  Numerical recipes in C. The art of scientific computing , 1987 .

[16]  K. J. Ray Liu,et al.  VLSI design of high-speed time-recursive 2-D DCT/IDCT processor for video applications , 1996, IEEE Trans. Circuits Syst. Video Technol..

[17]  M. Fratti,et al.  A novel architecture for VLSI implementation of the 2-D DCT/IDCT , 1992, [Proceedings] ICASSP-92: 1992 IEEE International Conference on Acoustics, Speech, and Signal Processing.

[18]  R.F. Woods,et al.  Novel VLSI implementation of (8×8) point 2-D DCT , 1994 .

[19]  Richard J. Kozick,et al.  Computation of discrete cosine transform using Clenshaw's recurrence formula , 1995, IEEE Signal Processing Letters.

[20]  Alan N. Willson,et al.  A 100 MHz 2-D 8×8 DCT/IDCT processor for HDTV applications , 1995, IEEE Trans. Circuits Syst. Video Technol..

[21]  Lee-Sup Kim,et al.  A 200 MHz 13 mm/sup 2/ 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme , 1994 .

[22]  H. C. Karathanasis,et al.  A low ROM distributed arithmetic implementation of the forward/inverse DCT/DST using rotations , 1995 .

[23]  Ephraim Feig,et al.  Fast algorithms for the discrete cosine transform , 1992, IEEE Trans. Signal Process..