The silicon insulated-gate field-effect transistor

The device discussed in this paper represents a significant departure from the conventional unipolar transistor in that the reverse-biased p-n junction has been superseded by a Metal-Oxide-Semiconductor (MOS) control structure. This structure can be used to enhance as well as deplete the charge near the surface of the semiconductor. A simple model is proposed and the basic transistor current-voltage relationships are derived for the case of a thick oxide and shallow conducting channel. This case is in contrast to the p-n junction-type described by Shockley, the latter being analogous to a very thin oxide and a deep uniformly doped channel. A more detailed model is subsequently proposed in order to explain some experimentally observed anomalies for units not adequately described by the simpler model. In particular, the usual approximation of constant current in the saturation region is abandoned and consideration is given to the behavior of the drain resistance in this region. It is found that the relations predicting and describing this behavior are closely analogous to similar relations for vacuum tubes. Experimental data from units to which this model may be applied has shown close agreement with the theoretical predictions. Breakdown in the channel is also investigated and found to be a double-valued function of the gate voltage. For low-gate voltages the breakdown is induced directly by the drain-to-source field and occurs across the constricted portion of the channel near the drain. For higher-gate voltages carrier generation is induced directly by the gate-to-drain field with the source-to-drain sweep field acting to remove the impact ionized and/or field emitted carriers. Brief consideration is also given to the question of the validity of using Boltzmann or Fermi-Dirac statistics in devices which are not necessarily in thermal equilibrium. The use of these statistics to predict the formation of a gate-field-induced inversion layer at the oxide-silicon interface in typical depletion-type transistors is found to be unjustified. This is due to generation and flow rate limitations on the source of the carriers which form this layer, and contrasts with the case of the induced channel-type unit for which the use of these statistics appears justified. Experimental evidence regarding saturation and complete pinch-off of drain current has indicated that the inversion layer does, in fact, fail to exist, as predicted, for the depletion-type transistor. Units fabricated to date have the following typical characteristics: input impedance, 7 µµf, 10+15ohms; transconductance, 2000 µmhos; cutoff bias,-7 volts (depletion unit); rise time, 10 nsec. The yield of units has averaged over 95 per cent on recently fabricated wafers, indicating great promise for integrated electronics applications.