On Multiple Path Propagating Tests for Path Delay Faults

The path delay fault model is arguably the strongest model for real delay defects in circuits. The recent availability of fully path delay fult testable designs has made it feasible to consider the problem of making test application for path delay faults more efficient by reducing the sizes of the potentially large test-sets required to obtain satisfactory coverages. This paper presents, for the first time, a heuristic-driven test generation procedure for obtaining maximal multiple-path-propagating robust tests, which detect the largest possible number of path faults simultaneously. Extensive experimental results are presented to demonstrate the efficacy of this approach, which is seen to significantly reduce test-set lengths for path delay faults by generating highly efficient robust tests.

[1]  Gordon L. Smith,et al.  Model for Delay Faults Based upon Paths , 1985, ITC.

[2]  John J. Shedletsky,et al.  An Experimental Delay Test Generator for LSI Logic , 1980, IEEE Transactions on Computers.

[3]  Barry K. Rosen,et al.  Delay test generation. I. Concepts and coverage metrics , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[4]  S. M. Reddy,et al.  On the design of path delay fault testable combinational circuits , 1990, [1990] Digest of Papers. Fault-Tolerant Computing: 20th International Symposium.

[5]  Sudhakar M. Reddy,et al.  On the fault coverage of delay fault detecting tests , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

[6]  Sudhakar M. Reddy,et al.  On the computation of the ranges of detected delay fault sizes , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[7]  Robert K. Brayton,et al.  MIS: A Multiple-Level Logic Optimization System , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Kaushik Roy,et al.  Synthesis of delay fault testable combinational logic , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[9]  Robert A. Rasmussen,et al.  Delay test generation , 1977, DAC '77.

[10]  Yashwant K. Malaiya,et al.  Testing for Timing Faults in Synchronous Sequential Integrated Circuits , 1983, International Test Conference.

[11]  S. Reddy,et al.  Synthesis of combinational logic circuits for path delay fault testability , 1990, IEEE International Symposium on Circuits and Systems.

[12]  Sreejit Chakravarty.  A testable realization of CMOS combinational circuits , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[13]  Sudhakar M. Reddy,et al.  On the detection of delay faults , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.

[14]  Kurt Keutzer,et al.  On properties of algebraic transformation and the multifault testability of multilevel logic , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[15]  Yashwant K. Malaiya,et al.  Modeling and Testing for Timing Faults in Synchronous Sequential Circuits , 1984, IEEE Design & Test of Computers.

[16]  Sudhakar M. Reddy,et al.  On the design of robust testable CMOS combinational logic circuits , 1988, [1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

[17]  Michael H. Schulz,et al.  Advanced automatic test pattern generation techniques for path delay faults , 1989, [1989] The Nineteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

[18]  Sudhakar M. Reddy,et al.  Design of robustly testable combinational logic circuits , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[19]  Sudhakar M. Reddy,et al.  On Delay Fault Testing in Logic Circuits , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[20]  Jacob Savir,et al.  Random Pattern Testability of Delay Faults , 1988, IEEE Trans. Computers.

[21]  John A. Waicukauski,et al.  On computing the sizes of detected delay faults , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[22]  Bertrand Serlet.  Fast, Small, and Static Combinatorial CMOS Circuits , 1987, 24th ACM/IEEE Design Automation Conference.

[23]  Kenneth D. Wagner,et al.  The Error Latency of Delay Faults in Combinational and Sequential Circuits , 1985, ITC.