Power Management for GPU-CPU Heterogeneous Systems
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[1] Hyesoon Kim,et al. An integrated GPU power and performance model , 2010, ISCA.
[2] Wenguang Chen,et al. MapCG: Writing parallel program portable between CPU and GPU , 2010, 2010 19th International Conference on Parallel Architectures and Compilation Techniques (PACT).
[3] Guibin Wang,et al. Power-Efficient Work Distribution Method for CPU-GPU Heterogeneous System , 2010, International Symposium on Parallel and Distributed Processing with Applications.
[4] Arnaud Tisserand,et al. Power Consumption of GPUs from a Software Perspective , 2009, ICCS.
[5] Tran Ngoc Minh,et al. Modeling Parallel System Workloads with Temporal Locality , 2009, JSSPP.
[6] Margaret Martonosi,et al. Formal online methods for voltage/frequency control in multiple clock domain microprocessors , 2004, ASPLOS XI.
[7] Sanjay Ghemawat,et al. MapReduce: Simplified Data Processing on Large Clusters , 2004, OSDI.
[8] Kevin Skadron,et al. Rodinia: A benchmark suite for heterogeneous computing , 2009, 2009 IEEE International Symposium on Workload Characterization (IISWC).
[9] Gagan Agrawal,et al. Compiler and runtime support for enabling generalized reduction computations on heterogeneous parallel configurations , 2010, ICS '10.
[10] David R. Kaeli,et al. Exploiting Memory Access Patterns to Improve Memory Performance in Data-Parallel Architectures , 2011, IEEE Transactions on Parallel and Distributed Systems.
[11] Diana Marculescu,et al. Variation-aware dynamic voltage/frequency scaling , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.
[12] José González,et al. Meeting points: Using thread criticality to adapt multicore hardware to parallel regions , 2008, 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT).
[13] Hyesoon Kim,et al. Qilin: Exploiting parallelism on heterogeneous multiprocessors with adaptive mapping , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
[14] Mahmut T. Kandemir,et al. Exploiting barriers to optimize power consumption of CMPs , 2005, 19th IEEE International Parallel and Distributed Processing Symposium.
[15] Samuel Williams,et al. Roofline: an insightful visual performance model for multicore architectures , 2009, CACM.
[16] Michael C. Huang,et al. The thrifty barrier: energy-aware synchronization in shared-memory multiprocessors , 2004, 10th International Symposium on High Performance Computer Architecture (HPCA'04).
[17] Ulrich Kremer,et al. The design, implementation, and evaluation of a compiler algorithm for CPU energy reduction , 2003, PLDI '03.