Delay oriented design methodology: application to the design of a VHF low power VLSI polyphase oscillator

A new design methodology (Delay Oriented Design-DOD) has been developed in order to design a novel oscillator architecture. A 250 MHz DOD oscillator has been implemented on a 0.8 /spl mu/m, two metal layers standard VLSI CMOS technology. It provides both in-phase and quadrature-phase differential outputs on a 60 MHz frequency range. The measured phase noise at 1 kHz offset from the carrier is about -92 dBc/Hz. The oscillator current consumption is 3 mA on a 3.3 V voltage supply.

[1]  J.G. Maneatis,et al.  Low-jitter and process independent DLL and PLL based on self biased techniques , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[2]  Ali Hajimiri,et al.  A general theory of phase noise in electrical oscillators , 1998 .

[3]  A. Brunnschweiler,et al.  A propagation-delay expression and its application to the optimization of polysilicon emitter ECL processes , 1988 .

[4]  Behzad Razavi,et al.  A study of phase noise in CMOS oscillators , 1996, IEEE J. Solid State Circuits.

[5]  T. Saito,et al.  Novel high-speed and low-power dynamic MOS flip-flops for a low-power 1.25GHz multiplexer/demultiplexer , 1997, Proceedings of the 23rd European Solid-State Circuits Conference.

[6]  W. Fang.  Accurate analytical delay expressions for ECL and CML circuits and their applications to optimizing high-speed bipolar circuits , 1990 .

[7]  Michiel Steyaert,et al.  A 1.8-GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors , 1997, IEEE J. Solid State Circuits.

[8]  J. Fenk,et al.  An up-conversion loop transmitter IC for digital mobile telephones , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).