论文信息 - On Formal Equivalence Verification of Hardware

On Formal Equivalence Verification of Hardware

When modeling the logic functionality, hardware can be viewed as a Finite State Machine (FSM) [7]. The power-up state of hardware cannot be determined uniquely, therefore the FSM modeling the hardware does not have an initial state (or a set of initial states). Instead, it has a set of legal operation states, and it must be brought into this set of operation states from any power-up state by a reboot sequence.

Zurab Khasidashvili | Z. Khasidashvili

[1] Zurab Khasidashvili,et al. TRANS: efficient sequential verification of loop-free circuits , 2002, Seventh IEEE International High-Level Design Validation and Test Workshop, 2002..

[2] Zurab Khasidashvili,et al. Theoretical framework for compositional sequential hardware equivalence verification in presence of design constraints , 2004, ICCAD 2004.

[3] Niraj K. Jha,et al. Switching and Finite Automata Theory , 2010 .

[4] Zurab Khasidashvili,et al. Seqver : A Sequential Equivalence Verifier for Hardware Designs , 2006, 2006 International Conference on Computer Design.

[5] Edmund M. Clarke,et al. Model Checking , 1999, Handbook of Automated Reasoning.

[6] In-Ho Moon,et al. A compositional approach to the combination of combinational and sequential equivalence checking of circuits without known reset states , 2007 .

[7] Zurab Khasidashvili,et al. Post-reboot Equivalence and Compositional Verification of Hardware , 2006, 2006 Formal Methods in Computer Aided Design.

[8] Carl Pixley,et al. A theory and implementation of sequential hardware equivalence , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9] Shi-Yu Huang,et al. Formal Equivalence Checking and Design Debugging , 1998 .

[10] Edward A. Feigenbaum,et al. Switching and Finite Automata Theory: Computer Science Series , 1990 .