Digital post-correction of front-end track-and-hold circuits in ADCs

This paper presents the design of a digitally post-corrected open-loop front-end track-and-hold circuit for a pipelined ADC. An open-loop architecture has been selected to achieve high-speed and low power-consumption. Clock-boosting, resistive source-degeneration and cross-coupling are used to reduce low-order harmonic distortion. To further reduce distortion components in the open-loop circuit, a new digital post-correction algorithm is proposed together with a built-in self-measurement technique

[1]  A.H.M. van Roermund,et al.  A CMOS V-I converter with 75-dB SFDR and 360-/spl mu/W power consumption , 2005, IEEE Journal of Solid-State Circuits.

[2]  Ding-Lan Shen,et al.  A linear-approximation technique for digitally-calibrated pipelined A/D converters , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[3]  A. Karanicolas,et al.  A 15-b 1-Msample/s digitally self-calibrated pipeline ADC , 1993 .

[4]  H. Voorman,et al.  Tunable high-frequency Gm-C filters , 2000, IEEE Journal of Solid-State Circuits.

[5]  P. Gray,et al.  A 1 . 5V , 10-bit , 14 . 3-MS / s CMOS Pipeline Analog-to-Digital Converter , 1999 .

[6]  Arthur H. M. van Roermund,et al.  A flexible ADC approach for mixed-signal SoC platforms , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[7]  Arun Ravindran,et al.  Digital error correction and calibration of gain non-linearities in a pipelined ADC , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[8]  P. R. Gray,et al.  A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter , 1999, IEEE J. Solid State Circuits.

[9]  B. Murmann,et al.  A 12 b 75 MS/s pipelined ADC using open-loop residue amplification , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..