Non-surjective finite alphabet iterative decoders

This paper introduces a new theoretical framework, akin to the use of imprecise message storage in Low Density Parity Check (LDPC) decoders, which is seen as an enabler for cost-effective hardware designs. The proposed framework is the one of Non-Surjective Finite Alphabet Iterative Decoders (NS-FAIDs), and it is shown to provide a unified approach for several designs previously proposed in the literature. NS-FAIDs are optimized by density evolution for WiMAX irregular LDPC codes and we show they provide different trade-offs between hardware complexity and decoding performance. In particular, we derive a set of 27 NS-FAIDs that provide decoding gains up to 0.36 dB, while yielding a memory/interconnect reduction up to 25%/30% compared to the Min-Sum decoder.

[1]  Ajay Dholakia,et al.  Reduced-complexity decoding of LDPC codes , 2005, IEEE Transactions on Communications.

[2]  David Declercq,et al.  Channel coding : theory, algorithms, and applications , 2014 .

[3]  David Declercq,et al.  Finite alphabet iterative decoders for LDPC codes surpassing floating-point iterative decoders , 2011 .

[4]  Ieee Microwave Theory,et al.  Part 16: Air Interface for Fixed and Mobile Broadband Wireless Access Systems — Amendment for Physical and Medium Access Control Layers for Combined Fixed and Mobile Operation in Licensed Bands , 2003 .

[5]  Vikram Arkalgud Chandrasetty,et al.  An area efficient LDPC decoder using a reduced complexity min-sum algorithm , 2012, Integr..

[6]  Sridhar Rajagopal,et al.  Low-power dual quantization-domain decoding for LDPC codes , 2014, 2014 IEEE Global Communications Conference.

[7]  David Declercq,et al.  Code-aware quantizer design for finite-precision min-sum decoders , 2016, 2016 IEEE International Black Sea Conference on Communications and Networking (BlackSeaCom).

[8]  Rüdiger L. Urbanke,et al.  The capacity of low-density parity-check codes under message-passing decoding , 2001, IEEE Trans. Inf. Theory.

[9]  David Declercq,et al.  Iterative decoding beyond belief propagation , 2010, 2010 Information Theory and Applications Workshop (ITA).

[10]  Valentin Savin,et al.  Chapter 4 – LDPC Decoders , 2014 .

[11]  Zhongfeng Wang,et al.  A Memory Efficient Partially Parallel Decoder Architecture for Quasi-Cyclic LDPC Codes , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[12]  Keshab K. Parhi,et al.  Min-Sum Decoder Architectures With Reduced Word Length for LDPC Codes , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[13]  David Declercq,et al.  FPGA design of high throughput LDPC decoder based on imprecise Offset Min-Sum decoding , 2015, 2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS).

[14]  Guido Masera,et al.  Chapter 13 – Hardware Design and Realization for Iteratively Decodable Codes , 2014 .

[15]  Chin-Long Wey,et al.  Algorithms of Finding the First Two Minimum Values and Their Hardware Implementation , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[16]  David Declercq,et al.  Finite Alphabet Iterative Decoders—Part I: Decoding Beyond Belief Propagation on the Binary Symmetric Channel , 2013, IEEE Transactions on Communications.