Comprehensive Functional Verification: The Complete Industry Cycle

One of the biggest challenges in chip and system design is determining whether the hardware works correctly. That is the job of functional verification engineers and they are the audience for this comprehensive text from three top industry professionals. As designs increase in complexity, so has the value of verification engineers within the hardware design team. In fact, the need for skilled verification engineers has grown dramatically--functional verification now consumes between 40 and 70% of a project's labor, and about half its cost. Currently there are very few books on verification for engineers, and none that cover the subject as comprehensively as this text. A key strength of this book is that it describes the entire verification cycle and details each stage. The organization of the book follows the cycle, demonstrating how functional verification engages all aspects of the overall design effort and how individual cycle stages relate to the larger design process. Throughout the text, the authors leverage their 35 plus years experience in functional verification, providing examples and case studies, and focusing on the skills, methods, and tools needed to complete each verification task. Additionally, the major vendors (Mentor Graphics, Cadence Design Systems, Verisity, and Synopsys) have implemented key examples from the text and made these available on line, so that the reader can test out the methods described in the text. * Comprehensive overview of the complete verification cycle * Combines industry experience with a strong emphasis on functional verification fundamentals * Includes real-world case studies and downloadable software implementations of key examples from the major vendors (Mentor Graphics, Cadence Design Systems, Verisity, and Synopsys) Table of Contents Part I: Introduction to Verification Chapter 1: Verification in the Chip Design Process Chapter 2: Verification Flow Chapter 3: Fundamentals of Simulation Based Verification Chapter 4: The Verification Plan Part II: Simulation-Based Verification Chapter 5: HDLs and Simulation Engines Chapter 6: Creating Environments Chapter 7: Strategies for Simulation-based Stimulus Generation Chapter 8: Strategies for Results Checking in Chapter 9: Pervasive Function Verification Chapter 10: Re-Use Strategies and System Simulation Part III: Formal Verification Chapter 11 Introduction to Formal Verification Chapter 12 Using Formal Verification Part IV: Comprehensive Verification Chapter 13: Completing the Verification Cycle Chapter 14: Advanced Verification Techniques Part V: Case Studies Chapter 15: Case Studies Glossary References

[1]  Barry K. Rosen,et al.  HSS--A High-Speed Simulator , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  Daniel Geist,et al.  AVPGEN-A test generator for architecture verification , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[3]  Steven Skiena,et al.  The Algorithm Design Manual , 2020, Texts in Computer Science.

[4]  Avi Ziv,et al.  Probabilistic regression suites for functional verification , 2004, Proceedings. 41st Design Automation Conference, 2004..

[5]  Wolfgang Kunz,et al.  SAT and ATPG: Boolean engines for formal hardware verification , 2002, ICCAD 2002.

[6]  Bob Bentley,et al.  Validating the Intel(R) Pentium(R) 4 microprocessor , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[7]  Avi Ziv,et al.  Using a constraint satisfaction formulation and solution techniques for random test program generation , 2002, IBM Syst. J..

[8]  Ilan Beer,et al.  FoCs: Automatic Generation of Simulation Checkers from Formal Specifications , 2000, CAV.

[9]  Michael Kantrowitz,et al.  I'm done simulating; now what? Verification coverage analysis and correctness checking of the DEC chip 21164 Alpha microprocessor , 1996, DAC '96.

[10]  Eiji Fujiwara,et al.  Single b-bit byte error correcting and double bit error detecting codes for high-speed memory systems , 1992, [1992] Digest of Papers. FTCS-22: The Twenty-Second International Symposium on Fault-Tolerant Computing.

[11]  Mark R. Greenstreet,et al.  Formal verification in hardware design: a survey , 1999, TODE.

[12]  Jason Baumgartner,et al.  Automatic formal verification of fused-multiply-add FPUs , 2005, Design, Automation and Test in Europe.

[13]  J. Paul Roth,et al.  Techniques for the diagnosis of switching circuit failures , 1961, SWCT.

[14]  Michael Yoeli,et al.  Methodology and System for Practical Formal Verification of Reactive Hardware , 1994, CAV.

[15]  Ieee Standards Board IEEE standard verilog hardware description language , 2001 .

[16]  Kenneth L. McMillan,et al.  Symbolic model checking: an approach to the state explosion problem , 1992 .

[17]  Arvind Srinivasan,et al.  Verity - A formal verification program for custom CMOS circuits , 1995, IBM J. Res. Dev..

[18]  Armin Biere,et al.  Symbolic Model Checking without BDDs , 1999, TACAS.

[19]  Hans Eveking,et al.  Verifikation digitaler Systeme , 1991 .

[20]  Janick Bergeron,et al.  Writing Testbenches: Functional Verification of HDL Models, Second Edition , 2003 .

[21]  Louise Trevillyan,et al.  EDA in IBM: past, present, and future , 2000, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[22]  Philip R. Moorby,et al.  The Verilog Hardware Description Language, 5th Edition , 2002 .

[23]  J. S. Liptay,et al.  Design of the IBM Enterprise System/9000 high-end processor , 1992, IBM J. Res. Dev..

[24]  Mike Bartley,et al.  A comparison of three verification techniques: directed testing, pseudo-random testing and property checking , 2002, DAC '02.

[25]  Orna Kupferman,et al.  Coverage metrics for formal verification , 2003, International Journal on Software Tools for Technology Transfer.

[26]  Malay K. Ganai,et al.  Circuit-based Boolean reasoning , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[27]  Samir Palnitkar Design Verification with e , 2003 .

[28]  Avi Ziv,et al.  Hole analysis for functional coverage data , 2002, DAC '02.

[29]  Karem A. Sakallah,et al.  GRASP—a new search algorithm for satisfiability , 1996, ICCAD 1996.

[30]  Dominik Stoffel,et al.  Reasoning in Boolean Networks - Logic Synthesis and Verification Using Testing Techniques , 1997, Frontiers in electronic testing.

[31]  Rolf Drechsler,et al.  Advanced Formal Verification , 2004 .

[32]  Avi Ziv,et al.  Coverage directed test generation for functional verification using Bayesian networks , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[33]  Bruce Wile Designer-level verification using TIMEDIAG/GENRAND , 1997, IBM J. Res. Dev..

[34]  Shmuel Ur,et al.  Micro architecture coverage directed generation of test programs , 1999, DAC '99.

[35]  David M. Russinoff A Mechanically Checked Proof of IEEE Compliance of the Floating Point Multiplication, Division and Square Root Algorithms of the AMD-K7™ Processor , 1998, LMS J. Comput. Math..

[36]  Robert K. Brayton,et al.  Implicit state enumeration of finite state machines using BDD's , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[37]  Eugene Goldberg,et al.  BerkMin: A Fast and Robust Sat-Solver , 2002 .

[38]  Yoav Hollander,et al.  The e language: a fresh separation of concerns , 2001, Proceedings Technology of Object-Oriented Languages and Systems. TOOLS 38.

[39]  Jeffrey D. Ullman,et al.  Introduction to Automata Theory, Languages and Computation , 1979 .

[40]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[41]  Edsger W. Dijkstra,et al.  Notes on structured programming , 1970 .

[42]  Avi Ziv,et al.  User defined coverage—a tool supported methodology for design verification , 1998, DAC.

[43]  C. L. Berman,et al.  Functional comparison of logic designs for VLSI circuits , 1989, ICCAD 1989.

[44]  Jianwen Zhu,et al.  Specification and Design of Embedded Systems , 1998, Informationstechnik Tech. Inform..

[45]  Thorsten Grotker,et al.  System Design with SystemC , 2002 .

[46]  Peter J. Ashenden,et al.  The Designer's Guide to VHDL , 1995 .

[47]  Edmund M. Clarke,et al.  Symbolic model checking for sequential circuit verification , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[48]  Serdar Tasiran,et al.  Formal verification meets simulation (embedded tutorial) (abstract only) , 1999, ICCAD '99.

[49]  Donald W. Loveland,et al.  A machine program for theorem-proving , 2011, CACM.

[50]  Sofiène Tahar,et al.  A survey on system-on-a-chip design languages , 2003, The 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications, 2003. Proceedings..

[51]  Sharad Malik,et al.  Chaff: engineering an efficient SAT solver , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[52]  C. L. Chen,et al.  Fault-tolerance design of the IBM Enterprise System/9000 Type 9021 processors , 1992, IBM J. Res. Dev..