Sub micron CMOS features are attractive for Polysilicon Electrical Fuse (E-Fuse) repair options in VLSI designs. E-Fuse implementations as contrasted to laser fuses provide large density advantages over laser fusing and allows for the repair of packaged die, thus providing substantial final yield benefits. Laser fusing typically requires keep out design rules such that fuse neighbors are not unintentionally programmed from a misaligned laser source. Additionally laser fuses typically require a protective cavity to act as a programming debris reservoir. These reasons as well as improving upon the fuse repair solutions required to manage reliability and yield of large die [1] are the major driving forces for providing E-Fuse solutions. In this paper we describe a case study to optimize E-Fuse long term reliability. The methodology employed is for a Tungsten Silicide E-Fuse (WSi/sub 2/), but the intention of this paper is to benchmark a qualification plan that can be employed for any E-Fuse, i.e. polysilicon, metal, or anti-fuse qualification.