Memory based architecture and its implementation scheme named bit-parallel block-parallel functional memory type parallel processor BPBP FMPP

Abstract According to the progress of VLSI technology, the integration of memory and logic circuits on the same chip is becoming a key technology of the high performance processors. This paper, proposes a concept of new Memory Based Architecture (MBA) and presents one of its application-specific implementations. The MBA has a memory based two-dimensional regular, high density array structure capable of performing SIMD type parallel operations. The MBA inherits features of different implementation schemes proposed so far and varying from the content addressable memory to the memory processor array. As an example of MBA realization we propose a Bit-Parallel Block-Parallel Functional Memory type Processor (BPBP FMPP) and its application specific type FMPP-VQ developed for vector quantization. The BPBP FMPP is a set of memory-processing units capable of computing arithmetic and logic operations on two words simultaneously on every unit. The FMPP-VQ computes the distances between an input vector and all reference vectors in parallel and outputs the minimum value of the distances. It accelerates the nearest-neighbor search of vector quantization. An experimental LSI which operates at 25 MHz clock frequency has been fabricated.

[1]  V. Cuperman,et al.  Vector quantization: A pattern-matching technique for speech coding , 1983, IEEE Communications Magazine.

[2]  Keikichi Tamaru,et al.  The Trend of Functional Memory Development (Special Issue on LSI Memories) , 1993 .

[3]  H. Onodera,et al.  A Memory-based Parallel Processor for Vector Quantization , 1996, ESSCIRC '96: Proceedings of the 22nd European Solid-State Circuits Conference.

[4]  Duncan G. Elliott,et al.  Computational Ram: A Memory-simd Hybrid And Its Application To Dsp , 1992, 1992 Proceedings of the IEEE Custom Integrated Circuits Conference.

[5]  R. M. Lea,et al.  A 9-kbit associative memory for high-speed parallel processing applications , 1988 .

[6]  Hiroto Yasuura,et al.  A Bit-Parallel Block-Parallel Functional Memory Type Parallel Processor Architecture (Special Issue on New Architecture LSIs) , 1993 .

[7]  Robert M. Gray,et al.  An Algorithm for Vector Quantizer Design , 1980, IEEE Trans. Commun..

[8]  L. Kohn,et al.  A 1,000,000 transistor microprocessor , 1989, IEEE International Solid-State Circuits Conference, 1989 ISSCC. Digest of Technical Papers.

[9]  R. Gray,et al.  Vector quantization , 1984, IEEE ASSP Magazine.

[10]  Alan W. Paeth,et al.  DEVELOPING PIXEL-PLANES, A SMART MEMORY-BASED RASTER GRAPHICS SYSTEM. , 1982 .

[11]  Yoshihiro Fujita,et al.  Design of 1.28-GB/s high bandwidth 2-Mb SRAM for integrated memory array processor applications , 1995 .

[12]  J. T. Koo Integrated-circuit content-addressable memories , 1970 .

[13]  T. Ogura,et al.  A 4-Kbit associative memory LSI , 1985, IEEE Journal of Solid-State Circuits.