论文信息 - Modeling, design and characterization of a new low jitter analog dual tuning LC-VCO PLL architecture

Modeling, design and characterization of a new low jitter analog dual tuning LC-VCO PLL architecture

This paper describes the modeling, design and characterization of a low jitter 2.4 GHz LC-VCO PLL architecture realized in a standard 0.12 /spl mu/m CMOS technology. It features very low VCO gain for noise rejection and it is equipped with an automatic analog calibration of the VCO curve. Measurements show the integrated jitter to be 0.74 ps, that is 43% lower with respect to a standard PLL topology which has same bandwidth and same output frequency range, build for comparison on the same wafer. The circuit area is 0.7 mm/sup 2/ (less then 1% larger than the reference PLL) and the power consumption is 32 mW (1% higher).

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