Tunnel FET‐based ultralow‐power and hardware‐secure circuit design considering p‐i‐n forward leakage

[1]  Ihsan Pehlivan,et al.  A novel high speed Artificial Neural Network–based chaotic True Random Number Generator on Field Programmable Gate Array , 2018, Int. J. Circuit Theory Appl..

[2]  A. T. Tiedemann,et al.  Complementary Strained Si GAA Nanowire TFET Inverter With Suppressed Ambipolarity , 2016, IEEE Electron Device Letters.

[3]  David Esseni,et al.  Essential Physics of the OFF-State Current in Nanoscale MOSFETs and Tunnel FETs , 2015, IEEE Transactions on Electron Devices.

[4]  Ru Huang,et al.  Design and Simulation of a Novel Graded-Channel Heterojunction Tunnel FET With High ${I} _{\scriptscriptstyle\text {ON}}/{I} _{\scriptscriptstyle\text {OFF}}$ Ratio and Steep Swing , 2017, IEEE Electron Device Letters.

[5]  E. Memišević,et al.  Vertical InAs/GaAsSb/GaSb tunneling field-effect transistor on Si with S = 48 mV/decade and Ion = 10 μA/μm for Ioff = 1 nA/μm at Vds = 0.3 V , 2016, 2016 IEEE International Electron Devices Meeting (IEDM).

[6]  Ching-Te Chuang,et al.  Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices , 2014, IEEE Transactions on Circuits and Systems I: Regular Papers.

[7]  Ken Mai,et al.  A secure camouflaged logic family using post-manufacturing programming with a 3.6GHz adder prototype in 65nm CMOS at 1V nominal VDD , 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).

[8]  Pierpaolo Palestri,et al.  Experimental characterization of the static noise margins of strained silicon complementary tunnel-FET SRAM , 2017, 2017 47th European Solid-State Device Research Conference (ESSDERC).

[9]  Bahniman Ghosh,et al.  Improved performance of a junctionless tunnel field effect transistor with a Si and SiGe heterostructure for ultra low power applications , 2015 .

[10]  Narayanan Vijaykrishnan,et al.  Tunnel FET RF Rectifier Design for Energy Harvesting Applications , 2014, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[11]  Michael Niemier,et al.  Analog Circuit Design Using Tunnel-FETs , 2015, IEEE Transactions on Circuits and Systems I: Regular Papers.

[12]  N. Guenifi,et al.  Rigorous Study of Double Gate Tunneling Field Effect Transistor Structure Based on Silicon , 2018, Materials Focus.

[13]  David Blaauw,et al.  14.2 A physically unclonable function with BER <10−8 for robust chip authentication using oscillator collapse in 40nm CMOS , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[14]  A. Zaslavsky,et al.  A Review of Sharp-Switching Devices for Ultra-Low Power Applications , 2016, IEEE Journal of the Electron Devices Society.

[15]  Hao Lu,et al.  Universal analytic model for tunnel FET circuit simulation , 2015 .

[16]  Juan Núñez,et al.  Impact of the RT-level architecture on the power performance of tunnel transistor circuits , 2018, Int. J. Circuit Theory Appl..

[17]  Ian A. Young,et al.  Design of Low Voltage Tunneling-FET Logic Circuits Considering Asymmetric Conduction Characteristics , 2014, IEEE Journal on Emerging and Selected Topics in Circuits and Systems.

[18]  Maria J. Avedillo,et al.  Comparative Analysis of Projected Tunnel and CMOS Transistors for Different Logic Application Areas , 2016, IEEE Transactions on Electron Devices.

[19]  David Blaauw,et al.  An All-Digital Edge Racing True Random Number Generator Robust Against PVT Variations , 2016, IEEE Journal of Solid-State Circuits.

[20]  Michael Niemier,et al.  Tunnel FET Current Mode Logic for DPA-Resilient Circuit Designs , 2017, IEEE Transactions on Emerging Topics in Computing.

[21]  Trond Ytterdal,et al.  Universal TFET model , 2015 .

[22]  Sudhir Satpathy,et al.  A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS , 2017, IEEE Journal of Solid-State Circuits.

[23]  Jun Rim Choi,et al.  Tunneling Field Effect Transistors for Enhancing Energy Efficiency and Hardware Security of IoT Platforms: Challenges and Opportunities , 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS).

[24]  Swaroop Ghosh,et al.  Spintronics and Security: Prospects, Vulnerabilities, Attack Models, and Preventions , 2016, Proceedings of the IEEE.

[25]  Ashish Tiwari,et al.  Reverse Engineering Digital Circuits Using Structural and Functional Analyses , 2014, IEEE Transactions on Emerging Topics in Computing.

[26]  M. J. Kumar,et al.  Controlling the Drain Side Tunneling Width to Reduce Ambipolar Current in Tunnel FETs Using Heterodielectric BOX , 2015, IEEE Transactions on Electron Devices.

[27]  Christof Paar,et al.  Physical Design Obfuscation of Hardware: A Comprehensive Investigation of Device and Logic-Level Techniques , 2019, IEEE Transactions on Information Forensics and Security.

[28]  S. Strangio,et al.  Strained Silicon Complementary TFET SRAM: Experimental Demonstration and Simulations , 2018, IEEE Journal of the Electron Devices Society.

[29]  Michael T. Niemier,et al.  Enhancing hardware security with emerging transistor technologies , 2016, 2016 International Great Lakes Symposium on VLSI (GLSVLSI).

[30]  Michael T. Niemier,et al.  Using emerging technologies for hardware security beyond PUFs , 2016, 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[31]  K. Sri Rama Krishna,et al.  Designing energy efficient logic gates with Hetero junction Tunnel fets at 20nm , 2014, 2014 2nd International Conference on Devices, Circuits and Systems (ICDCS).

[32]  Anirban Sengupta.  Hardware Vulnerabilities and Their Effects on CE Devices: Design for Security Against Trojans [Hardware Matters] , 2017, IEEE Consumer Electronics Magazine.

[33]  Giovanni De Micheli,et al.  Emerging Technology-Based Design of Primitives for Hardware Security , 2016, JETC.

[34]  Luca Selmi,et al.  Impact of TFET Unidirectionality and Ambipolarity on the Performance of 6T SRAM Cells , 2015, IEEE Journal of the Electron Devices Society.

[35]  Stefan Mangard,et al.  Systematic Classification of Side-Channel Attacks: A Case Study for Mobile Devices , 2016, IEEE Communications Surveys & Tutorials.