Interface states in HfO/sub 2/ stacks with metal gate: nature, passivation, generation [MOS devices]

This paper investigates interface states in HfO/sub 2/ devices with metal gate. First we studied the nature of these defects. The Si/SiO/sub x/ interface of SiO/sub x//HfO/sub 2/ stacks is modified by RTP at high temperature but after a 900/spl deg/C RTP, it is similar to the Si interface of conventional SiO/sub 2/ capacitors. Moreover, we show that higher temperatures of forming gas anneals FGA (530/spl deg/C) are required to passivate interface defects of HfO/sub 2/ capacitor devices compared to SiO/sub 2/. In a complete MOSfet process flow, T=425/spl deg/C is however high enough to passivate interface states. Moreover, for the first time, we performed atomic H/sup 0/ plasma annealing of HfO/sub 2//TiN stacks which drastically reduces the Dit down to 2-3.10/sup 10//cm/sup 2//eV. The generation of interface states is finally investigated. The degradation of the interface does not depend on the initial density of Dit and partial recovery of Dit is observed after stress interruption. Higher device lifetimes in term of NBTI and breakdown are then expected for 530/spl deg/C FGA devices.

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