Performance, power and scalability analysis of HEVC interpolation filter using FPGAs

Motion compensation is the most time-consuming stage of the most recent video coding standard, and uses an interpolation filter to handle efficiently the video bitstream. When high resolutions, low power budgets and huge amount of video data are demanded, exploiting parallelism is a mandatory task. In this paper we propose an implementation of the interpolation filter using the reconfigurable hardware technology, in order to build parallel computing systems that offer a high performance, in terms of computing time and power consumption. The timing simulations and energy analysis performed on different devices show that the on-chip replication of the filter provides high speedups with regard to general purpose processors. The good experimental results motivates us to do a first approach to scalable parallel computing systems where parallelism is exploited from fine to coarse grain, multiplying the speedups obtained. In particular, we propose an on-chip multiprocessor system where filters act as coprocessors of embedded high-performance and low-power microprocessors, linked among them by point-to-point buses. This on-chip architecture can be applied to high performance computing systems based on the same reconfigurable hardware technology.