论文信息 - Low-power programmable high-gain time difference amplifier with regeneration time control

Low-power programmable high-gain time difference amplifier with regeneration time control

A gain controllable SR-latch-based time difference amplifier (TDA) with a gain of up to 150 by controlling the regeneration time constant, especially with programmable transconductance ( g m ), is presented. The presented g m control uses resistor degeneration at the input switches so that the effective g m is reduced, whereas the time difference gain increases. Unavoidable large crowbar current from the slow regeneration is avoided by shifting to the fast regeneration mode after regeneration is completed, which effectively reduces current consumption by 29.3%.

[1] Gordon W. Roberts,et al. A CMOS time amplifier for Femto-second resolution timing measurement , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[2] Makoto Ikeda,et al. Cascaded Time Difference Amplifier using Differential Logic Delay Cell , 2009, 2009 International SoC Design Conference (ISOCC).

[3] A.A. Abidi,et al. A Low-Noise Wideband Digital Phase-Locked Loop Based on a Coarse–Fine Time-to-Digital Converter With Subpicosecond Resolution , 2009, IEEE Journal of Solid-State Circuits.

[4] Jae-Yoon Sim,et al. A high-gain wide-input-range time amplifier with an open-loop architecture and a gain equal to current bias ratio , 2011, IEEE Asian Solid-State Circuits Conference 2011.

[5] Gordon W. Roberts,et al. Digital storage, addition and subtraction of time-mode variables , 2011 .

[6] A.A. Abidi,et al. A 9 b, 1.25 ps Resolution Coarse–Fine Time-to-Digital Converter in 90 nm CMOS that Amplifies a Time Residue , 2008, IEEE Journal of Solid-State Circuits.