A Hierarchical Permutation Cyclic Coding Strategy for Sensorless Capacitor Voltage Balancing in Modular Multilevel Converters

This paper presents a new sensorless capacitor voltage balancing strategy for modular multilevel converters (MMCs) to effectively balance the submodule capacitor voltages in a wide range of switching frequencies. The proposed strategy is realized via a balancing unit equipped with a hierarchical permutation cyclic coding (PCC) method to evenly distribute the switching gate signals among the submodules of each arm within a permutation time. The proposed strategy balances the submodule capacitor voltages to track their reference values with low voltage ripple in a wide range of switching frequencies. It remarkably enhances the converter system reliability, especially for a large number of submodules, because the need to measure the submodule capacitor voltages in each arm is eliminated. The proposed hierarchical PCC algorithm is decoupled from other standard control loops in an MMC. Digital time-domain simulation studies are conducted on a 21-level MMC to confirm the effectiveness of the proposed algorithm in high and low switching frequencies under balanced and unbalanced load conditions. In addition, the proposed method is implemented in the FPGA-based RT-LAB real-time simulator platform to validate its performance in a hardware-in-the-loop setup.