论文信息 - A New Architecture for an Automatic Generation of Fast Pipelined Adders

A New Architecture for an Automatic Generation of Fast Pipelined Adders

This paper describes a compact VLSI implementation of fast pipelined adders. A new architecture is presented. Although the speed achieved is lineary proportionnai to o(n), it is faster than if it would be proportional to o(logn) (n equals to the number of bits). A new design strategy has been used to speed up the algorithm. In addition, the whole set of blocks has been designed in order to allow an automatic generation of any size of adders.

D. Mlynek | J. Kowalczuk | S. Tudor

[1] H. Oguey,et al. CODYMOS frequency dividers achieve low power consumption and high frequency , 1973 .

[2] Christer Svensson,et al. A true single-phase-clock dynamic CMOS circuit technique , 1987 .

[3] H. T. Kung,et al. A Regular Layout for Parallel Adders , 1982, IEEE Transactions on Computers.

[4] Christer Svensson,et al. High-speed CMOS circuit technique , 1989 .

[5] Algirdas Avizienis,et al. Signed-Digit Numbe Representations for Fast Parallel Arithmetic , 1961, IRE Trans. Electron. Comput..

[6] N. F. Goncalves,et al. NORA: a racefree dynamic CMOS technique for pipelined logic structures , 1983 .