AMF-Placer: High-Performance Analytical Mixed-size Placer for FPGA

To enable the performance optimization of application mapping on modern field-programmable gate arrays (FPGAs), certain critical path portions of the designs might be prearranged into many multi-cell macros during synthesis. These movable macros with constraints of shape and resources lead to challenging mixed-size placement for FPGA designs which cannot be addressed by previous works of analytical placers. In this work, we propose AMF-Placer, an open-source Analytical Mixed-size FPGA placer supporting mixed-size placement on FPGA, with an interface to Xilinx Vivado. To speed up the convergence and improve the quality of the placement, AMF-Placer is equipped with a series of new techniques for wirelength optimization, cell spreading, packing, and legalization. Based on a set of the latest large open-source benchmarks from various domains for Xilinx Ultrascale FPGAs, experimental results indicate that AMF-Placer can improve HPWL by 20.4%-89.3% and reduce runtime by 8.0%-84.2%, compared to the baseline. Furthermore, utilizing the parallelism of the proposed algorithms, with 8 threads, the placement procedure can be accelerated by 2.41x on average.

[1]  Jason Cong,et al.  Hardware Acceleration of Long Read Pairwise Overlapping in Genome Sequencing: A Race Between FPGA and GPU , 2019, 2019 IEEE 27th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

[2]  David Z. Pan,et al.  A New Paradigm for FPGA Placement Without Explicit Packing , 2019, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[3]  Tao Lin,et al.  POLAR 3.0: An ultrafast global placement engine , 2015, 2015 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[4]  Stephen Yang,et al.  Routability-Driven FPGA Placement Contest , 2016, ISPD.

[5]  Dirk Stroobandt,et al.  Accelerating FPGA Routing Through Algorithmic Enhancements and Connection-aware Parallelization , 2020, ACM Trans. Reconfigurable Technol. Syst..

[6]  Chris Lavin,et al.  RapidWright: Enabling Custom Crafted Implementations for FPGAs , 2018, 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

[7]  Norbert Wehn,et al.  Hardware architecture of Bidirectional Long Short-Term Memory Neural Network for Optical Character Recognition , 2017, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017.

[8]  Ulf Schlichtmann,et al.  Kraftwerk2—A Fast Force-Directed Quadratic Placement Approach Using an Accurate Net Model , 2008, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[9]  Andreas Herkersdorf,et al.  Open Tiled Manycore System-on-Chip , 2013, ArXiv.

[10]  Tao Lin,et al.  POLAR 2.0: An effective routability-driven placer , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

[11]  David Z. Pan,et al.  elfPlace: Electrostatics-based Placement for Large-Scale Heterogeneous FPGAs , 2019, 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[12]  Kevin E. Murray,et al.  VTR 8: High Performance CAD and Customizable FPGA Architecture Modelling , 2020 .

[13]  Jason Weston,et al.  End-To-End Memory Networks , 2015, NIPS.

[14]  Gary William Grewal,et al.  GPlace: A congestion-aware placement tool for UltraScale FPGAs , 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[15]  Brent E. Nelson,et al.  HMFlow: Accelerating FPGA Compilation with Hard Macros for Rapid Prototyping , 2011, 2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines.

[16]  Yuan Zhou,et al.  Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs , 2018, FPGA.

[17]  J. Cong,et al.  Simultaneous placement with clustering and duplication , 2004 .

[18]  Igor L. Markov,et al.  ComPLx: A competitive primal-dual Lagrange optimization for global placement , 2012, DAC Design Automation Conference 2012.

[19]  Marcel Gort,et al.  Analytical placement for heterogeneous FPGAs , 2012, 22nd International Conference on Field Programmable Logic and Applications (FPL).

[20]  Yao-Wen Chang,et al.  Efficient and effective packing and analytical placement for large-scale heterogeneous FPGAs , 2014, 2014 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[21]  Elias Vansteenkiste,et al.  Liquid: High quality scalable placement for large heterogeneous FPGAs , 2017, 2017 International Conference on Field Programmable Technology (ICFPT).

[22]  Dongjin Lee,et al.  SimPL: An Effective Placement Algorithm , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[23]  Evangeline F. Y. Young,et al.  RippleFPGA: A routability-driven placement for large-scale heterogeneous FPGAs , 2016, 2016 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[24]  Ümit V. Çatalyürek,et al.  PaToH: Partitioning Tool for Hypergraphs , 1999 .

[25]  Jan M. Van Campenhout,et al.  Generating new benchmark designs using a multi-terminal net model , 1999, Integr..

[26]  Yao-Wen Chang,et al.  Clock-aware placement for large-scale heterogeneous FPGAs , 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[27]  David Z. Pan,et al.  UTPlaceF: A Routability-Driven FPGA Placer With Physical and Congestion Aware Packing , 2018, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[28]  David Wentzlaff,et al.  OpenPiton: An Open Source Manycore Research Framework , 2016, ASPLOS.