A High-Speed Radix-64 Parallel Multiplier Using a Novel Hardware Implementation Approach for Partial Product Generation Based on Redundant Binary Arithmetic

A high-speed radix-64 parallel multiplier using novel reduced delay partial product generator is proposed. The use of radix-64 Booth encoder and selector for partial product generation by Sang-Hoon (Sang-Hoon Lee et al., 2002) reduces the number of partial product rows by six fold. The Booth selector selects one among X, 2X, 3X, 4X, 8X, 16X, 24X and 32X where X is the multiplicand. Before selection 3X computation must be completed which accounts for maximum delay because of carry propagation or carry look ahead addition of X and 2X. In this work this fundamental coefficient is generated as 4X-X using redundant binary (RB) arithmetic. This leads to zero delay for 3X computation as well as simplifies the partial product rows accumulation. This novel method of partial product generation decreases delay by 24% in comparison to last high-speed reported parallel multiplier (Sang-Hoon Lee et al., 2002) using radix-64 Booth encoding.

[1]  A. Inoue,et al.  A 4.1 ns compact 54/spl times/54 b multiplier utilizing sign select Booth encoders , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[2]  Makoto Suzuki,et al.  A 4.4 ns CMOS 54/spl times/54-b multiplier using pass-transistor multiplexer , 1995 .

[3]  Chein-Wei Jen,et al.  High-Speed Booth Encoded Parallel Multiplier Design , 2000, IEEE Trans. Computers.

[4]  W. Rulling.  A remark on carry-free binary multiplication , 2003 .

[5]  K. Mashiko,et al.  An 8.8-ns 54/spl times/54-bit multiplier with high speed redundant binary architecture , 1996 .

[6]  G. De Micheli,et al.  Circuit and architecture trade-offs for high-speed multiplication , 1991 .

[7]  Hong-June Park,et al.  A Compact Radix-64 54 54 CMOS Redundant Binary Parallel Multiplier , 2002 .

[8]  Luigi Ciminiera,et al.  Carry-Save Multiplication Schemes without Final Addition , 1996, IEEE Trans. Computers.

[9]  Bang-Sup Song,et al.  A carry-free 54b/spl times/54b multiplier using equivalent bit conversion algorithm , 2001 .

[10]  Algirdas Avizienis,et al.  Signed-Digit Numbe Representations for Fast Parallel Arithmetic , 1961, IRE Trans. Electron. Comput..

[11]  Atsuki Inoue,et al.  A 4.1-ns Compact 54 54-b Multiplier Utilizing Sign-Select Booth Encoders , 1997 .

[12]  G. Goto,et al.  A 54*54-b regularly structured tree multiplier , 1992 .

[13]  Hiroto Yasuura,et al.  High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree , 1985, IEEE Transactions on Computers.

[14]  Bang-Sup Song,et al.  A carry-free 54 b/spl times/54 b multiplier using equivalent bit conversion algorithm , 2000, Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434).