Tv image signal compensating circuit

The video signal compensation apparatus comprises a frame signal output for generating a frame signal dividing one frame into field; an address counter for generating a field memory address; a read/write controller for controlling recording and decoding data; a memory read address generator for generating a memory read address of previous line and existing line; an address input switch for selectively converting the read/write address and providing a field memory with the read/write address; a field memory for storing or decoding the output video data of an A/D converter; an output switch for selectively outputting video data stored in the memory; and a compensation operator for interpolating scanning line of 3:4 picture to a scanning line of 9:16 picture. The apparatus prevents the picture from being distorted.