Optimisation of Ivy Bridge topography

The article presents a quasi-optimum placement of different functional modules in an integrated circuit. The goal of quasi-optimum placement is minimization of maximum chip temperature. Firstly, a RC thermal model of the microprocessor packages is presented. Based on package's geometry and chip lloor topography the HotSpot calculates different parameters for RC thermal model. A New topography of Ivy Bridge processor was modelled using a simple heuristic approach. Therefore, its temperature profile was compared to that obtained through original published floor plan. The crated floor plan provides lower chip maximal temperature than original published one.

[1]  Andrzej Napieralski,et al.  Influence of Scaling on IC Temperature in FinFET Microprocessor Technologies , 2013, Proceedings of the 20th International Conference Mixed Design of Integrated Circuits and Systems - MIXDES 2013.

[2]  Andrzej Napieralski,et al.  Modelling electronic circuit radiation cooling using analytical thermal model , 2000 .

[3]  Andrzej Kos.  Temperature Computations in Power Microcircuits , 1993 .

[4]  Application of RC Equivalent Networks to Modelling of Nonlinear Thermal Phenomena , 2007, 2007 14th International Conference on Mixed Design of Integrated Circuits and Systems.

[5]  Kevin Skadron,et al.  Temperature-aware microarchitecture , 2003, ISCA '03.

[6]  Andrzej Kos,et al.  INVESTIGATION OF HEAT TRANSFER IN INTEGRATED CIRCUITS , 2014 .

[7]  D. Schweitzer.  Generation of multisource dynamic compact thermal models by RC-network optimization , 2013, 29th IEEE Semiconductor Thermal Measurement and Management Symposium.

[8]  Pinaki Mazumder,et al.  Accelerated Chip-Level Thermal Analysis Using Multilayer Green's Function , 2007, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[9]  G. De Mey,et al.  Thermal Placement in Hybrid Circuits—A Heuristic Approach , 1994 .